Add root cell, inmate cell and Linux demo cell configuration files for NXP
LS1088ARDB platform.
Signed-off-by: Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
---
configs/arm64/ls1088a-rdb-inmate-demo.c | 128 ++++++
configs/arm64/ls1088a-rdb-linux-demo.c | 148 +++++++
configs/arm64/ls1088a-rdb.c | 513 ++++++++++++++++++++++++
3 files changed, 789 insertions(+)
create mode 100644 configs/arm64/ls1088a-rdb-inmate-demo.c
create mode 100644 configs/arm64/ls1088a-rdb-linux-demo.c
create mode 100644 configs/arm64/ls1088a-rdb.c
diff --git a/configs/arm64/ls1088a-rdb-inmate-demo.c
b/configs/arm64/ls1088a-rdb-inmate-demo.c
new file mode 100644
index 00000000..3caee05d
--- /dev/null
+++ b/configs/arm64/ls1088a-rdb-inmate-demo.c
@@ -0,0 +1,128 @@
+/*
+ * Configuration for LS1088ARDB board - inmate demo
+ *
+ * Copyright NXP 2021
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[8];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "inmate-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 81 - 32,
+
+ .console = {
+ .address = 0x21c0600,
+ .divider = 0xbd,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_1,
+ },
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70e000,
+ .virt_start = 0xfb70e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* DUART1 */ {
+ .phys_start = 0x21c0000,
+ .virt_start = 0x21c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /* GIC-400 */ {
+ .address = 0x6000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0,
+ 1 << (81 - 64),
+ 0,
+ 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 1,
+ .shmem_peers = 1,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ },
+};
diff --git a/configs/arm64/ls1088a-rdb-linux-demo.c
b/configs/arm64/ls1088a-rdb-linux-demo.c
new file mode 100644
index 00000000..ee8b18e9
--- /dev/null
+++ b/configs/arm64/ls1088a-rdb-linux-demo.c
@@ -0,0 +1,148 @@
+/*
+ * Configuration for LS1088ARDB - linux-demo
+ *
+ * Copyright 2021 NXP
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[14];
+ struct jailhouse_irqchip irqchips[1];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "linux-inmate-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 81 - 32,
+ },
+
+ .cpus = {
+ 0xc,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xfb70e000,
+ .virt_start = 0xfb70e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* IVSHMEM shared memory regions for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xfb800000, 1),
+ /* DUART1 */ {
+ .phys_start = 0x21c0000,
+ .virt_start = 0x21c0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* clockgen */ {
+ .phys_start = 0x01300000,
+ .virt_start = 0x01300000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* RAM */ {
+ .phys_start = 0xbf900000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0xc0000000,
+ .size = 0x3b500000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /* GIC-400 */ {
+ .address = 0x6000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0,
+ 1 << (81 - 64) | 1 << (82 - 64) |
+ 1 << (83 - 64) | 1 << (88 - 64),
+ 0,
+ 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 2,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ { /* IVSHMEM 00:01.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 5,
+ .shmem_dev_id = 1,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/configs/arm64/ls1088a-rdb.c b/configs/arm64/ls1088a-rdb.c
new file mode 100644
index 00000000..cb93df1e
--- /dev/null
+++ b/configs/arm64/ls1088a-rdb.c
@@ -0,0 +1,513 @@
+/*
+ * Configuration for LS1088ARDB board
+ *
+ * Copyright 2021 NXP
+ *
+ * Authors:
+ * Anda-Alexandra Dorneanu <anda.-alexandra.dorne...@nxp.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[63];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xfba00000,
+ .size = 0x00400000,
+ },
+ .debug_console = {
+ .address = 0x21c0500,
+ .size = 0x100,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_1,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x13000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = -1,
+
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x6000000,
+ .gicr_base = 0x6100000,
+ .gicc_base = 0xc0c0000,
+ .gich_base = 0xc0d0000,
+ .gicv_base = 0xc0e0000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "ls1088a",
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .vpci_irq_base = 114 - 32,
+ },
+ },
+
+ .cpus = {
+ 0xff,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xfb700000,
+ .virt_start = 0xfb700000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xfb701000,
+ .virt_start = 0xfb701000,
+ .size = 0x9000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xfb70a000,
+ .virt_start = 0xfb70a000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ {
+ .phys_start = 0xfb70c000,
+ .virt_start = 0xfb70c000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xfb70e000,
+ .virt_start = 0xfb70e000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* IVSHMEM shared memory regions for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xfb800000, 0),
+ /* RAM - 1GB - root cell */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x40000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* DRAM2 */ {
+ .phys_start = 0x8080000000,
+ .virt_start = 0x8080000000,
+ .size = 0x180000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* RAM: Inmate */ {
+ .phys_start = 0xc0000000,
+ .virt_start = 0xc0000000,
+ .size = 0x3b500000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* clockgen */ {
+ .phys_start = 0x01300000,
+ .virt_start = 0x01300000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dcfg */ {
+ .phys_start = 0x01e00000,
+ .virt_start = 0x01e00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* rcpm */ {
+ .phys_start = 0x01e30000,
+ .virt_start = 0x01e30000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* rst */ {
+ .phys_start = 0x01e60000,
+ .virt_start = 0x01e60000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* isc */ {
+ .phys_start = 0x01f70000,
+ .virt_start = 0x01f70000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* tmu */ {
+ .phys_start = 0x01f80000,
+ .virt_start = 0x01f80000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* dspi0 */ {
+ .phys_start = 0x02100000,
+ .virt_start = 0x02100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* duart0 */ {
+ .phys_start = 0x021c0000,
+ .virt_start = 0x021c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio0 */ {
+ .phys_start = 0x02300000,
+ .virt_start = 0x02300000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio1 */ {
+ .phys_start = 0x02310000,
+ .virt_start = 0x02310000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio2 */ {
+ .phys_start = 0x02320000,
+ .virt_start = 0x02320000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* gpio3 */ {
+ .phys_start = 0x02330000,
+ .virt_start = 0x02330000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ifc */ {
+ .phys_start = 0x02240000,
+ .virt_start = 0x02240000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* ftm0 */ {
+ .phys_start = 0x02800000,
+ .virt_start = 0x02800000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c0 */ {
+ .phys_start = 0x02000000,
+ .virt_start = 0x02000000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c1 */ {
+ .phys_start = 0x02010000,
+ .virt_start = 0x02010000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c2 */ {
+ .phys_start = 0x02020000,
+ .virt_start = 0x02020000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* i2c3 */ {
+ .phys_start = 0x02030000,
+ .virt_start = 0x02030000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* qspi */ {
+ .phys_start = 0x020c0000,
+ .virt_start = 0x020c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* esdhc0 */ {
+ .phys_start = 0x02140000,
+ .virt_start = 0x02140000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* usb0 */ {
+ .phys_start = 0x03100000,
+ .virt_start = 0x03100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* usb1 */ {
+ .phys_start = 0x03110000,
+ .virt_start = 0x03110000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sata0 */ {
+ .phys_start = 0x03200000,
+ .virt_start = 0x03200000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* its */ {
+ .phys_start = 0x6020000,
+ .virt_start = 0x6020000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* crypto */ {
+ .phys_start = 0x08000000,
+ .virt_start = 0x08000000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie1 */ {
+ .phys_start = 0x03400000,
+ .virt_start = 0x03400000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 */ {
+ .phys_start = 0x03500000,
+ .virt_start = 0x03500000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie3 */ {
+ .phys_start = 0x03600000,
+ .virt_start = 0x03600000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie1 pf0 */ {
+ .phys_start = 0x034c0000,
+ .virt_start = 0x034c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 pf0 */ {
+ .phys_start = 0x035c0000,
+ .virt_start = 0x035c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie3 pf0 */ {
+ .phys_start = 0x036c0000,
+ .virt_start = 0x036c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie1 host bridge */ {
+ .phys_start = 0x2000000000,
+ .virt_start = 0x2000000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie2 host bridge */ {
+ .phys_start = 0x2800000000,
+ .virt_start = 0x2800000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* pcie3 host bridge */ {
+ .phys_start = 0x3000000000,
+ .virt_start = 0x3000000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog0 */ {
+ .phys_start = 0x0c000000,
+ .virt_start = 0x0c000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog1 */ {
+ .phys_start = 0x0c010000,
+ .virt_start = 0x0c010000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog2 */ {
+ .phys_start = 0x0c020000,
+ .virt_start = 0x0c020000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog3 */ {
+ .phys_start = 0x0c030000,
+ .virt_start = 0x0c030000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog4 */ {
+ .phys_start = 0x0c100000,
+ .virt_start = 0x0c100000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog5 */ {
+ .phys_start = 0x0c110000,
+ .virt_start = 0x0c110000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog6 */ {
+ .phys_start = 0x0c120000,
+ .virt_start = 0x0c120000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wdog7 */ {
+ .phys_start = 0x0c130000,
+ .virt_start = 0x0c130000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* mc */ {
+ .phys_start = 0x08340000,
+ .virt_start = 0x08340000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wriop ni */ {
+ .phys_start = 0x08800000,
+ .virt_start = 0x08800000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wriop config space */ {
+ .phys_start = 0x08b80000,
+ .virt_start = 0x08b80000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wriop ports */ {
+ .phys_start = 0x08c00000,
+ .virt_start = 0x08c00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* mc portals */ {
+ .phys_start = 0x80c000000,
+ .virt_start = 0x80c000000,
+ .size = 0x4000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* qbman portals */ {
+ .phys_start = 0x818000000,
+ .virt_start = 0x818000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* wriop access window */ {
+ .phys_start = 0x4300000000,
+ .virt_start = 0x4300000000,
+ .size = 0x100000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* peb */ {
+ .phys_start = 0x4c00000000,
+ .virt_start = 0x4c00000000,
+ .size = 0x400000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x06000000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ /* GIC */ {
+ .address = 0x06000000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ },
+
+ .pci_devices = {
+ { /* IVSHMEM 00:00.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ { /* IVSHMEM 00:01.0 */
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 0,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX,
+ .shmem_regions_start = 5,
+ .shmem_dev_id = 0,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.17.1
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