Initializing Jailhouse hypervisor v0.12 (294-g6af5edf-dirty) on CPU 7
Code location: 0xfffffffff0000050
Using x2APIC
Page pool usage after early setup: mem 134/32207, remap 0/131072
Initializing processors:
CPU 7... (APIC ID 38) OK
CPU 4... (APIC ID 32) OK
CPU 5... (APIC ID 34) OK
CPU 6... (APIC ID 36) OK
CPU 1... (APIC ID 2) OK
CPU 0... (APIC ID 0) OK
CPU 2... (APIC ID 4) OK
CPU 3... (APIC ID 6) OK
Initializing unit: VT-d
DMAR unit @0xfbffe000/0x1000
DMAR unit @0xdfffc000/0x1000
Reserving 24 interrupt(s) for device 00:1f.7 at index 0
Reserving 24 interrupt(s) for device 00:05.4 at index 24
Reserving 24 interrupt(s) for device 80:05.4 at index 48
Initializing unit: IOAPIC
Initializing unit: Cache Allocation Technology
Initializing unit: PCI
Adding PCI device 00:00.0 to cell "RootCell"
Adding virtual PCI device 00:17.0 to cell "RootCell"
Adding virtual PCI device 00:18.0 to cell "RootCell"
Adding PCI device 00:01.0 to cell "RootCell"
Reserving 2 interrupt(s) for device 00:01.0 at index 72
Adding PCI device 00:01.1 to cell "RootCell"
Reserving 2 interrupt(s) for device 00:01.1 at index 74
Adding PCI device 00:03.0 to cell "RootCell"
Reserving 2 interrupt(s) for device 00:03.0 at index 76
Adding PCI device 00:03.2 to cell "RootCell"
Reserving 2 interrupt(s) for device 00:03.2 at index 78
Adding PCI device 00:05.0 to cell "RootCell"
Adding PCI device 00:05.2 to cell "RootCell"
Adding PCI device 00:05.4 to cell "RootCell"
Adding PCI device 00:11.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 00:11.0 at index 80
Adding PCI device 00:1a.0 to cell "RootCell"
Adding PCI device 00:1c.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 00:1c.0 at index 81
Adding PCI device 00:1c.1 to cell "RootCell"
Reserving 1 interrupt(s) for device 00:1c.1 at index 82
Adding PCI device 00:1c.3 to cell "RootCell"
Reserving 1 interrupt(s) for device 00:1c.3 at index 83
Adding PCI device 00:1d.0 to cell "RootCell"
Adding PCI device 00:1e.0 to cell "RootCell"
Adding PCI device 00:1f.0 to cell "RootCell"
Adding PCI device 00:1f.2 to cell "RootCell"
Reserving 1 interrupt(s) for device 00:1f.2 at index 84
Adding PCI device 00:1f.3 to cell "RootCell"
Adding PCI device 06:00.0 to cell "RootCell"
Reserving 5 interrupt(s) for device 06:00.0 at index 85
Adding PCI device 07:00.0 to cell "RootCell"
Reserving 5 interrupt(s) for device 07:00.0 at index 90
Adding PCI device 08:00.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 08:00.0 at index 95
Adding PCI device 09:00.0 to cell "RootCell"
Adding PCI device 7f:08.0 to cell "RootCell"
Adding PCI device 7f:09.0 to cell "RootCell"
Adding PCI device 7f:0a.0 to cell "RootCell"
Adding PCI device 7f:0a.1 to cell "RootCell"
Adding PCI device 7f:0a.2 to cell "RootCell"
Adding PCI device 7f:0a.3 to cell "RootCell"
Adding PCI device 7f:0b.0 to cell "RootCell"
Adding PCI device 7f:0b.3 to cell "RootCell"
Adding PCI device 7f:0c.0 to cell "RootCell"
Adding PCI device 7f:0c.1 to cell "RootCell"
Adding PCI device 7f:0d.0 to cell "RootCell"
Adding PCI device 7f:0d.1 to cell "RootCell"
Adding PCI device 7f:0e.0 to cell "RootCell"
Adding PCI device 7f:0e.1 to cell "RootCell"
Adding PCI device 7f:0f.0 to cell "RootCell"
Adding PCI device 7f:0f.1 to cell "RootCell"
Adding PCI device 7f:0f.2 to cell "RootCell"
Adding PCI device 7f:0f.3 to cell "RootCell"
Adding PCI device 7f:0f.4 to cell "RootCell"
Adding PCI device 7f:0f.5 to cell "RootCell"
Adding PCI device 7f:10.0 to cell "RootCell"
Adding PCI device 7f:10.1 to cell "RootCell"
Adding PCI device 7f:10.2 to cell "RootCell"
Adding PCI device 7f:10.3 to cell "RootCell"
Adding PCI device 7f:10.4 to cell "RootCell"
Adding PCI device 7f:10.5 to cell "RootCell"
Adding PCI device 7f:10.6 to cell "RootCell"
Adding PCI device 7f:10.7 to cell "RootCell"
Adding PCI device 7f:13.0 to cell "RootCell"
Adding PCI device 7f:13.1 to cell "RootCell"
Adding PCI device 7f:13.4 to cell "RootCell"
Adding PCI device 7f:13.5 to cell "RootCell"
Adding PCI device 7f:16.0 to cell "RootCell"
Adding PCI device 7f:16.1 to cell "RootCell"
Adding PCI device 7f:16.2 to cell "RootCell"
Adding PCI device 80:03.0 to cell "RootCell"
Reserving 2 interrupt(s) for device 80:03.0 at index 96
Adding PCI device 80:03.2 to cell "RootCell"
Reserving 2 interrupt(s) for device 80:03.2 at index 98
Adding PCI device 80:05.0 to cell "RootCell"
Adding PCI device 80:05.2 to cell "RootCell"
Adding PCI device 80:05.4 to cell "RootCell"
Adding PCI device ff:08.0 to cell "RootCell"
Adding PCI device ff:09.0 to cell "RootCell"
Adding PCI device ff:0a.0 to cell "RootCell"
Adding PCI device ff:0a.1 to cell "RootCell"
Adding PCI device ff:0a.2 to cell "RootCell"
Adding PCI device ff:0a.3 to cell "RootCell"
Adding PCI device ff:0b.0 to cell "RootCell"
Adding PCI device ff:0b.3 to cell "RootCell"
Adding PCI device ff:0c.0 to cell "RootCell"
Adding PCI device ff:0c.1 to cell "RootCell"
Adding PCI device ff:0d.0 to cell "RootCell"
Adding PCI device ff:0d.1 to cell "RootCell"
Adding PCI device ff:0e.0 to cell "RootCell"
Adding PCI device ff:0e.1 to cell "RootCell"
Adding PCI device ff:0f.0 to cell "RootCell"
Adding PCI device ff:0f.1 to cell "RootCell"
Adding PCI device ff:0f.2 to cell "RootCell"
Adding PCI device ff:0f.3 to cell "RootCell"
Adding PCI device ff:0f.4 to cell "RootCell"
Adding PCI device ff:0f.5 to cell "RootCell"
Adding PCI device ff:10.0 to cell "RootCell"
Adding PCI device ff:10.1 to cell "RootCell"
Adding PCI device ff:10.2 to cell "RootCell"
Adding PCI device ff:10.3 to cell "RootCell"
Adding PCI device ff:10.4 to cell "RootCell"
Adding PCI device ff:10.5 to cell "RootCell"
Adding PCI device ff:10.6 to cell "RootCell"
Adding PCI device ff:10.7 to cell "RootCell"
Adding PCI device ff:13.0 to cell "RootCell"
Adding PCI device ff:13.1 to cell "RootCell"
Adding PCI device ff:13.4 to cell "RootCell"
Adding PCI device ff:13.5 to cell "RootCell"
Adding PCI device ff:16.0 to cell "RootCell"
Adding PCI device ff:16.1 to cell "RootCell"
Adding PCI device ff:16.2 to cell "RootCell"
Page pool usage after late setup: mem 469/32207, remap 65549/131072
Activating hypervisor
Adding virtual PCI device 00:17.0 to cell "nuttx"
Shared memory connection established, peer cells:
"RootCell"
Adding virtual PCI device 00:18.0 to cell "nuttx"
Shared memory connection established, peer cells:
"RootCell"
Created cell "nuttx"
Page pool usage after cell creation: mem 1001/32207, remap 65549/131072
Cell "nuttx" can be loaded
CPU 3 received SIPI, vector 100
Started cell "nuttx"
FATAL: Unhandled VM-Exit, reason 2
qualification 0
vectoring info: 0 interrupt info: 0
RIP: 0x0000000100939685 RSP: 0x0000000100da4d28 FLAGS: 10006
RAX: 0x00000000000326a0 RBX: 0x0000000100da4d40 RCX: 0x000000000000003e
RDX: 0x000000000010a003 RSI: 0x000000000010a000 RDI: 0x0000000000104010
CS: 8 BASE: 0x0000000000000000 AR-BYTES: 2099 EFER.LMA 1
CR0: 0x0000000080010033 CR3: 0x0000000000102000 CR4: 0x00000000000326a0
EFER: 0x0000000000000500
Parking CPU 3 (Cell: "nuttx")
在2021年12月22日星期三 UTC+8 21:41:09<jiajun huang> 写道：
> nuttx.c
>
> #include <jailhouse/types.h>
> #include <jailhouse/cell-config.h>
>
> struct {
> struct jailhouse_cell_desc cell;
> __u64 cpus[1];
> struct jailhouse_memory mem_regions[9];
> struct jailhouse_cache cache_regions[1];
> struct jailhouse_irqchip irqchips[3];
> struct jailhouse_pio pio_regions[3];
> struct jailhouse_pci_device pci_devices[2];
> struct jailhouse_pci_capability pci_caps[0];
>
> } __attribute__((packed)) config = {
> .cell = {
> .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
> .revision = JAILHOUSE_CONFIG_REVISION,
> .name = "nuttx",
> .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
> .cpu_set_size = sizeof(config.cpus),
> .num_memory_regions = ARRAY_SIZE(config.mem_regions),
> .num_cache_regions = ARRAY_SIZE(config.cache_regions),
> .num_irqchips = ARRAY_SIZE(config.irqchips),
> .num_pio_regions = ARRAY_SIZE(config.pio_regions),
> .num_pci_devices = ARRAY_SIZE(config.pci_devices),
> .num_pci_caps = ARRAY_SIZE(config.pci_caps),
> .console = {
> .type = JAILHOUSE_CON_TYPE_8250,
> .flags = JAILHOUSE_CON_ACCESS_PIO,
> .address = 0x3f8,
> },
> },
>
> .cpus = {
> 0x8,
> },
>
> .mem_regions = {
> /* MemRegion: 57a000000-5d9ffffff : JAILHOUSE Inmate Memory */
> {
> .phys_start = 0x57a000000,
> .virt_start = 0x57a000000,
> .size = 0x1000,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
> },
> {
> .phys_start = 0x57a001000,
> .virt_start = 0,
> .size = 0x40000000,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE |
> JAILHOUSE_MEM_ROOTSHARED,
> },
> {
> .phys_start = 0x5ba001000,
> .virt_start = 0x5ba001000,
> .size = 0x4000,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
> },
> {
> .phys_start = 0x5ba005000,
> .virt_start = 0x5ba005000,
> .size = 0x4000,
> .flags = JAILHOUSE_MEM_READ| JAILHOUSE_MEM_WRITE |
> JAILHOUSE_MEM_ROOTSHARED,
> },
> /* communication region */ {
> .virt_start = 0x5ba010000,
> .size = 0x00001000,
> .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> JAILHOUSE_MEM_COMM_REGION,
> },
> JAILHOUSE_SHMEM_NET_REGIONS(0x5ba205000, 1),
> },
>
> .cache_regions = {
> {
> .start = 0,
> .size = 2,
> .type = JAILHOUSE_CACHE_L3,
> },
> },
>
> .irqchips = {
> /* IOAPIC 0, GSI base 0 */
> {
> .address = 0xfec00000,
> .id = 0x100ff,
> .pin_bitmap = {
> 0x000001
> },
> },
> /* IOAPIC 2, GSI base 24 */
> {
> .address = 0xfec01000,
> .id = 0x1002c,
> .pin_bitmap = {
> 0x000000
> },
> },
> /* IOAPIC 3, GSI base 48 */
> {
> .address = 0xfec40000,
> .id = 0x802c,
> .pin_bitmap = {
> 0x000000
> },
> },
> },
>
> .pio_regions = {
> /* Port I/O: 0020-0021 : pic1 */
> PIO_RANGE(0x20, 0x2),
> /* Port I/O: 00a0-00a1 : pic2 */
> PIO_RANGE(0xa0, 0x2),
> /* Port I/O: 03f8-03ff : serial */
> PIO_RANGE(0x3f8, 0x8),
> },
> .pci_devices = {
> {
> .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
> .iommu = 1,
> .domain = 0x0,
> .bdf = 0x17 << 3,
> .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
> .num_msix_vectors = 16,
> .shmem_regions_start = 0,
> .shmem_dev_id = 1,
> .shmem_peers = 2,
> .shmem_protocol = 0x0002,
> },
> {
> .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
> .iommu = 1,
> .domain = 0x0,
> .bdf = 0x18 << 3,
> .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
> .num_msix_vectors = 2,
> .shmem_regions_start = 5,
> .shmem_dev_id = 1,
> .shmem_peers = 2,
> .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
> },
> },
>
> .pci_caps = {
> },
> };
>
> 在2021年12月22日星期三 UTC+8 21:39:52<jiajun huang> 写道：
>
>> Dear Jailhouse community，
>> This bug occurred when I tried to start nuttx on a none-root cell on the
>> server. I added two ivshmem devices for nuttx. Below is my configuration
>> file. I am not sure if there is a problem with the mmio area in the
>> configuration file. What is the communication area? In addition, if
>> jailhouse runs in QEMU, can two virtual machines communicate with each
>> other through ivshmem-net?
>>
>> Below is my root-cell , nuttx configuration and log output from the port.
>>
>> Best regards,
>>
>> Jiajun Huang
>>
>>
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