Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
---
 configs/riscv/dts/qemu-linux-inmate.dts | 135 ++++++++++++++++++++++++
 configs/riscv/qemu-linux-demo.c         | 101 ++++++++++++++++++
 2 files changed, 236 insertions(+)
 create mode 100644 configs/riscv/dts/qemu-linux-inmate.dts
 create mode 100644 configs/riscv/qemu-linux-demo.c

diff --git a/configs/riscv/dts/qemu-linux-inmate.dts 
b/configs/riscv/dts/qemu-linux-inmate.dts
new file mode 100644
index 00000000..0fdbbac8
--- /dev/null
+++ b/configs/riscv/dts/qemu-linux-inmate.dts
@@ -0,0 +1,135 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) OTH Regensburg, 2022
+ *
+ * Authors:
+ *  Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+/dts-v1/;
+/ {
+       model = "Jailhouse cell on RISC-V";
+
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       chosen {
+               stdout-path = "/soc/uart@10000000:115200n8";
+               bootargs = "console=ttyS0 earlycon=sbi";
+               linux,initrd-start = <0x82000000>;
+               linux,initrd-end = <0x82200000>;
+       };
+
+       memory@80000000 {
+               device_type = "memory";
+               /* 63MiB @ 0x80000000 */
+               reg = <0x00000000 0x80000000>, <0x00000000 0x3f00000>;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <0x989680>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       reg = <1>;
+                       status = "okay";
+                       compatible = "riscv";
+                       riscv,isa = "rv64imafdcsu";
+                       mmu-type = "riscv,sv39";
+
+                       cpu0_intc: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               compatible = "riscv,cpu-intc";
+                       };
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       reg = <2>;
+                       status = "okay";
+                       compatible = "riscv";
+                       riscv,isa = "rv64imafdcsu";
+                       mmu-type = "riscv,sv39";
+
+                       cpu1_intc: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               compatible = "riscv,cpu-intc";
+                       };
+               };
+
+               cpu@2 {
+                       device_type = "cpu";
+                       reg = <0>;
+                       status = "disabled";
+                       compatible = "riscv";
+                       riscv,isa = "rv64imafdcsu";
+                       mmu-type = "riscv,sv39";
+
+                       dummy_intc: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                               compatible = "riscv,cpu-intc";
+                       };
+               };
+       };
+       soc {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "simple-bus";
+               ranges;
+
+               uart@10000000 {
+                       interrupts = <0x0a>;
+                       interrupt-parent = <&plic0>;
+                       clock-frequency = "\08@";
+                       reg = <0x00 0x10000000 0x00 0x100>;
+                       compatible = "ns16550a";
+                       status = "okay";
+               };
+
+               plic0: plic@c000000 {
+                       reg = <0x00 0xc000000 0x00 0x210000>;
+                       interrupts-extended = <
+                               &dummy_intc 11
+                               &dummy_intc 9
+                               &cpu0_intc 11
+                               &cpu0_intc 9
+                               &cpu1_intc 11
+                               &cpu1_intc 9
+                       >;
+                       interrupt-controller;
+                       compatible = "sifive,plic-1.0.0\0riscv,plic0";
+                       riscv,ndev = <0x35>;
+                       #interrupt-cells = <0x01>;
+                       #address-cells = <0x00>;
+               };
+
+               pci@30000000 {
+                       compatible = "pci-host-ecam-generic";
+                       device_type = "pci";
+                       bus-range = <0 0>;
+                       #interrupt-cells = <1>;
+                       reg = <0x0 0x30000000 0x0 0x10000000>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges = <
+                               0x1000000 0x00 0x00 0x00 0x3000000 0x00 0x10000
+                               0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 
0x40000000
+                               0x3000000 0x04 0x00 0x04 0x00 0x04 0x00>;
+
+                       interrupt-map-mask = <0>;
+                       interrupt-map = <0 0 0 1 &plic0 32 0>;
+               };
+       };
+};
diff --git a/configs/riscv/qemu-linux-demo.c b/configs/riscv/qemu-linux-demo.c
new file mode 100644
index 00000000..e1947125
--- /dev/null
+++ b/configs/riscv/qemu-linux-demo.c
@@ -0,0 +1,101 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for RISC-V Linux inmate on QEMU
+ *
+ * Copyright (c) OTH Regensburg 2022
+ *
+ * Authors:
+ *  Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+       struct jailhouse_cell_desc cell;
+       struct jailhouse_cpu cpus[2];
+       struct jailhouse_memory mem_regions[8];
+       struct jailhouse_irqchip irqchips[1];
+       struct jailhouse_pci_device pci_devices[0];
+} __attribute__((packed)) config = {
+       .cell = {
+               .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+               .revision = JAILHOUSE_CONFIG_REVISION,
+               .name = "linux-demo",
+               .flags = JAILHOUSE_CELL_PASSIVE_COMMREG |
+                       JAILHOUSE_CELL_TEST_DEVICE |
+                       JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
+
+               .num_cpus = ARRAY_SIZE(config.cpus),
+               .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+               .num_irqchips = ARRAY_SIZE(config.irqchips),
+               .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+               .console = {
+                       .type = JAILHOUSE_CON_TYPE_8250,
+                       .size = 0x1000,
+                       .address = 0x10000000,
+                       .flags = JAILHOUSE_CON_ACCESS_MMIO | 
JAILHOUSE_CON_REGDIST_1,
+               },
+
+               .vpci_irq_base = 32,
+       },
+
+       .cpus = {
+               {
+                       .phys_id = 1,
+               },
+               {
+                       .phys_id = 2,
+               },
+       },
+
+       .mem_regions = {
+               /* RAM low */ {
+                       .phys_start = 0xbf800000,
+                       .virt_start = 0x0,
+                       .size = 1 * 1024 * 1024,
+                       .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+                               JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+               },
+               /* communication region */ {
+                       .virt_start = 0x00100000,
+                       .size = 0x00001000,
+                       .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+                               JAILHOUSE_MEM_COMM_REGION,
+               },
+               /* RAM high */ {
+                       .phys_start = 0xbb800000,
+                       .virt_start = 0x80000000,
+                       .size = 64 * 1024 * 1024,
+                       .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+                               JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+               },
+               /* uart@fc001000 */ {
+                       .phys_start = 0x10000000,
+                       .virt_start = 0x10000000,
+                       .size = 0x1000,
+                       .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+                               JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
+               },
+               /* IVSHMEM shared memory regions (networking) */
+               JAILHOUSE_SHMEM_NET_REGIONS(0xbf900000, 1),
+       },
+
+       .pci_devices = {
+       },
+
+       .irqchips = {
+               /* PLIC */ {
+                       .address = 0xc000000,
+                       .pin_base = 0,
+                       .pin_bitmap = {
+                               (1 << 0xa), 0, 0, 0,
+                       },
+               },
+       },
+};
-- 
2.36.1

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