Hi All,

Answering my own question :) :

I have run the demo from https://github.com/siemens/jailhouse-images for 
Raspberry Pie and simply collected the output of "cat /proc/iomem" before 
running Jailhouse, then after enabling Jailhouse in the root cell and in a 
Linux non-root cell. From that output it looks like Jialhouse does 1:1 
mapping between IPAs and PAs.

On a platform with Zynq UltraScale+ MPSoC, onto which Jailhouse has been 
ported, I have experimented with memory accesses, trying to access from the 
root cell the memory allocated to a non-root Linux cell and the other way 
round - trying to access from the non-root Linux cell the memory allocated 
to the root cell only. As expected, in both cases I have got "Unhandled 
data write...FATAL: unhandled trap (exception class 0x24)", while the cells 
can happily read from/write into physical addresses belonging to their own 
memory regions specified in the respective cells configuration. This 
appears to confirm the use of the 2nd stage translations for restricting 
cells access to physical memory.    

Best Regards,

Yelena


On Monday, November 14, 2022 at 2:19:55 PM UTC Yelena Konyukh wrote:

> Hi All,
>
> I would be very grateful, if anyone could explain how Jailhouse on ARM64 
> architectures uses the 2nd stage MMU translation.
>
> It does look like Jailhouse uses the 2nd stage MMU translations  - for 
> example, t is easy to find in the code where such registers as VTCR_EL2 
> and VTTBR_EL2 are set. I am guessing that Jailhouse, as one would expect 
> from a hypervisor, uses 2nd stage translation to protect VMs (cells) from 
> accessing each others memory (unless a memory region is explicitly shared 
> with a root cell by specifying JAILHOUSE_MEM_ROOTSHARED). Is that so? 
> Could anyone confirm? How is IPA<->PA mapping is done for VMs? Is it 1-to-1 
> mapping (so that, in fact, PA equals IPA)?
>
> Thank you very much in advance
>
> Best Regards,
>
> Yelena
>

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