Hi, I'm sending SGI interrupts between cores with a gic-v3 and noticed that
it sometimes the interrupts were lost. After some tinkering I realised that
gicv3_inject_irq skips the interrupt if it is already in a the list. I'm
not sure this is correct but I expect that the if it is already in the list
but marked as active the pending bit should be set and return.
With the following change no SGI interrupt where dropped.
--- a/hypervisor/arch/arm-common/gic-v3.c
+++ b/hypervisor/arch/arm-common/gic-v3.c
@@ -566,8 +566,16 @@ static int gicv3_inject_irq(u16 irq_id, u16 sender)
* A strict phys->virt id mapping is used for SPIs, so this
test
* should be sufficient.
*/
- if ((u32)lr == irq_id)
+ if ((u32)lr == irq_id) {
+ /* if interrupt is active set pending bit. */
+ if ((lr & ICH_LR_PENDACTIVE) == ICH_LR_ACTIVE) {
+ lr |= ICH_LR_GROUP_BIT;
+ lr |= ICH_LR_PENDING;
+ gicv3_write_lr(n, lr);
+ return 0;
+ }
return -EEXIST;
+ }
}
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