Hi all,
I have an AMD Ryzen 2600 on a b450 motherboard. My goal is to run two non
root linux cells, however, as of right now, I'm not able to start any non
root linux cells.
First of all I don't receive an output from the cell (I do get output from
the apic-demo though), therefore I don't really know if they're even
crashing or not; this is the output I get from the hypervisor after
enabling the root cell and issuing the following command:
sudo jailhouse cell linux configs/x86/linux_guest1.cell
../buildroot-2023.11/output/images/bzImage -i
../buildroot-2023.11/output/images/rootfs.cpio
Adding PCI device ff:1f.7 to cell "linux-x86-demo"
Created cell "linux-x86-demo"
Page pool usage after cell creation: mem 336/32211, remap 16392/131072
Cell "linux-x86-demo" can be loaded
CPU 4 received SIPI, vector 100
CPU 3 received SIPI, vector 100
Started cell "linux-x86-demo"
After this the cell appears to be running in cell list, however I can't
seem to get any output to confirm that (I even set
JAILHOUSE_CELL_VIRTUAL_CONSOLE_ACTIVE, but nothing appears on the vrtual
console accessed via "jailhouse console -f"). I also tried adding -c
"console=ttyS0,115200".
At this point if I try to disable/shutdown the cell, the system freezes
requiring a hard reset.
Also, there seems to be a mismatch between the PCI bdf value in the log
above and the one in the cell's configuration. In both root and non root
cells i set .bdf = (0x0f << 3) for the IVSHMEM net device and the Root cell
correctly reports that ("Adding virtual PCI device 00:0f.0 to cell
"RootCell"").
If I understood correctly, once the cell works properly I won't need to set
the console anymore as I can assign an ip (-c "ip x.x.x.x" in the cell
linux command) and ssh to the cell, right?
I attach the root and non root cells' configurations in case they're
needed. I can provide both the root and non root cell's kernel .conf and
the buildroot configuration I used if needed.
Thank you for your time,
Michele
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
To view this discussion on the web visit
https://groups.google.com/d/msgid/jailhouse-dev/824bacc4-b7ae-47c9-878e-7203214b4fc3n%40googlegroups.com.
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2014-2017
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* Configuration for Gigabyte Technology Co., Ltd. B450 AORUS M
* created with '/usr/local/libexec/jailhouse/jailhouse config create --mem-hv 128M --mem-inmates 512M b450m_big.c'
*
* NOTE: This config expects the following to be appended to your kernel cmdline
* "memmap=0x68000000$0x3a000000"
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[50];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pio pio_regions[16];
struct jailhouse_pci_device pci_devices[39];
struct jailhouse_pci_capability pci_caps[116];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
.hypervisor_memory = {
.phys_start = 0x3a000000,
.size = 0x8000000,
},
.debug_console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO |
JAILHOUSE_CON_REGDIST_1,
},
.platform_info = {
.pci_mmconfig_base = 0xf8000000,
.pci_mmconfig_end_bus = 0x3f,
.x86 = {
.pm_timer_address = 0x808,
.vtd_interrupt_limit = 256,
},
},
.root_cell = {
.name = "RootCell",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
},
},
.cpus = {
0x0000000000000fff,
},
.mem_regions = {
/* IVSHMEM shared memory regions (networking) - guest1 */
JAILHOUSE_SHMEM_NET_REGIONS(0x61f00000, 0),
/* MemRegion: 42000000-61ffffff : JAILHOUSE Inmate Memory - original*/
/* MemRegion: 42000000-61efffff : JAILHOUSE Inmate Memory */
{
.phys_start = 0x42000000,
.virt_start = 0x42000000,
.size = 0x1ff00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 42000000-4a0fffff : JAILHOUSE Inmate Memory - guest1*/
/*{
.phys_start = 0x42000000,
.virt_start = 0x42000000,
.size = 0x8100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},*/
/* MemRegion: 00000000-0009ffff : System RAM */
{
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0xa0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 000f0000-000fffff : System ROM */
{
.phys_start = 0xf0000,
.virt_start = 0xf0000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 00100000-09cfffff : System RAM */
{
.phys_start = 0x100000,
.virt_start = 0x100000,
.size = 0x9c00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0a000000-0a1fffff : System RAM */
{
.phys_start = 0xa000000,
.virt_start = 0xa000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0a200000-0a209fff : ACPI Non-volatile Storage */
{
.phys_start = 0xa200000,
.virt_start = 0xa200000,
.size = 0xa000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 0a20a000-0affffff : System RAM */
{
.phys_start = 0xa20a000,
.virt_start = 0xa20a000,
.size = 0xdf6000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0b020000-39ffffff : System RAM */
{
.phys_start = 0xb020000,
.virt_start = 0xb020000,
.size = 0x2efe0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: a2000000-d7024fff : System RAM */
{
.phys_start = 0xa2000000,
.virt_start = 0xa2000000,
.size = 0x35025000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: d7026000-d8142fff : System RAM */
{
.phys_start = 0xd7026000,
.virt_start = 0xd7026000,
.size = 0x111d000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: d819a000-dbb12fff : System RAM */
{
.phys_start = 0xd819a000,
.virt_start = 0xd819a000,
.size = 0x3979000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: dbc63000-dbcdffff : ACPI Tables */
{
.phys_start = 0xdbc63000,
.virt_start = 0xdbc63000,
.size = 0x7d000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
// invalid read addr 0xdc19d80c
/* MemRegion: dbce0000 - dc200000 : ??? */ //part of ACPI non volatile storage
{
.phys_start = 0xdbce0000,
.virt_start = 0xdbce0000,
.size = 0x520000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: dc222000-dc222fff : MSFT0101:00 */
{
.phys_start = 0xdc222000,
.virt_start = 0xdc222000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: dc226000-dc226fff : MSFT0101:00 */
{
.phys_start = 0xdc226000,
.virt_start = 0xdc226000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
//error invalid read addr 0xdce25c18
/* MemRegion: dc241000 - dcebbfff : ??? */ //reserved but accessed
{
.phys_start = 0xdc241000,
.virt_start = 0xdc241000,
.size = 0xc7b000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: dcebc000-deffffff : System RAM */
{
.phys_start = 0xdcebc000,
.virt_start = 0xdcebc000,
.size = 0x2144000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: e0000000-efffffff : 0000:07:00.0 */
{
.phys_start = 0xe0000000,
.virt_start = 0xe0000000,
.size = 0x10000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f0000000-f01fffff : 0000:07:00.0 */
{
.phys_start = 0xf0000000,
.virt_start = 0xf0000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe200000-fe2fdfff : xhci-hcd */
{
.phys_start = 0xfe200000,
.virt_start = 0xfe200000,
.size = 0xfe000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe2ff000-fe2fffff : xhci-hcd */
{
.phys_start = 0xfe2ff000,
.virt_start = 0xfe2ff000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe300000-fe3fffff : ccp */
{
.phys_start = 0xfe300000,
.virt_start = 0xfe300000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe401000-fe401fff : ccp */
{
.phys_start = 0xfe401000,
.virt_start = 0xfe401000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe501000-fe503fff : 0000:04:00.0 */
{
.phys_start = 0xfe501000,
.virt_start = 0xfe501000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe504000-fe504fff : r8169 */
{
.phys_start = 0xfe504000,
.virt_start = 0xfe504000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe600000-fe67ffff : 0000:02:00.1 */
{
.phys_start = 0xfe600000,
.virt_start = 0xfe600000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe680000-fe69ffff : ahci */
{
.phys_start = 0xfe680000,
.virt_start = 0xfe680000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe6a0000-fe6a1fff : xhci-hcd */
{
.phys_start = 0xfe6a0000,
.virt_start = 0xfe6a0000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe6a3000-fe6a7fff : xhci-hcd */
{
.phys_start = 0xfe6a3000,
.virt_start = 0xfe6a3000,
.size = 0x5000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe700000-fe707fff : ICH HD audio */
{
.phys_start = 0xfe700000,
.virt_start = 0xfe700000,
.size = 0x8000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe708000-fe708fff : ahci */
{
.phys_start = 0xfe708000,
.virt_start = 0xfe708000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe800000-fe83ffff : 0000:07:00.0 */
{
.phys_start = 0xfe800000,
.virt_start = 0xfe800000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe860000-fe863fff : ICH HD audio */
{
.phys_start = 0xfe860000,
.virt_start = 0xfe860000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe900000-fe901fff : nvme */
{
.phys_start = 0xfe900000,
.virt_start = 0xfe900000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe903000-fe903fff : nvme */
{
.phys_start = 0xfe903000,
.virt_start = 0xfe903000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe904000-fe904fff : nvme */
{
.phys_start = 0xfe904000,
.virt_start = 0xfe904000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe905000-fe905fff : nvme */
{
.phys_start = 0xfe905000,
.virt_start = 0xfe905000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fec10000-fec10fff : pnp 00:05 */
{
.phys_start = 0xfec10000,
.virt_start = 0xfec10000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fec30000-fec30fff : AMDIF030:00 AMDIF030:00 */
{
.phys_start = 0xfec30000,
.virt_start = 0xfec30000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed00000-fed003ff : PNP0103:00 */
{
.phys_start = 0xfed00000,
.virt_start = 0xfed00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed80000-fed8ffff : reserved but accessed */
{
.phys_start = 0xfed80000,
.virt_start = 0xfed80000,
.size = 0x1000, //only to fed80fff enough for fed802b0 which is the error's address
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed81500-fed818ff : AMDI0030:00 AMDI0030:00 */
{
.phys_start = 0xfed81500,
.virt_start = 0xfed81500,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fedc0000-fedc0fff : pnp 00:05 */
{
.phys_start = 0xfedc0000,
.virt_start = 0xfedc0000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ff000000-ffffffff : pnp 00:05 */
{
.phys_start = 0xff000000,
.virt_start = 0xff000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 100000000-41fffffff : System RAM */
{
.phys_start = 0x100000000,
.virt_start = 0x100000000,
.size = 0x320000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 000c0000-000dffff : ROMs */
{
.phys_start = 0xc0000,
.virt_start = 0xc0000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
},
.irqchips = {
/* IOAPIC 13, GSI base 0 */
{
.address = 0xfec00000,
.id = 0xa0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 14, GSI base 24 */
{
.address = 0xfec01000,
.id = 0x1,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pio_regions = {
/* Port I/O: 0020-0021 : pic1 */
PIO_RANGE(0x20, 0x2),
/* Port I/O: 0040-0043 : timer0 */
PIO_RANGE(0x40, 0x4),
/* Port I/O: 0060-0060 : keyboard */
PIO_RANGE(0x60, 0x1),
/* Port I/O: 0061-0061 : PNP0800:00 */
PIO_RANGE(0x61, 0x1),
/* Port I/O: 0064-0064 : keyboard */
PIO_RANGE(0x64, 0x1),
/* Port I/O: 0070-0071 : rtc0 */
PIO_RANGE(0x70, 0x2),
/* Port I/O: 00a0-00a1 : pic2 */
PIO_RANGE(0xa0, 0x2),
/* Port I/O: 03f8-03ff : serial */
PIO_RANGE(0x3f8, 0x8),
/* Port I/O: 0800-0803 : ACPI PM1a_EVT_BLK */
PIO_RANGE(0x800, 0x4),
/* Port I/O: 0810-0815 : ACPI CPU throttle */
PIO_RANGE(0x810, 0x6),
/* Port I/O: 0820-0827 : ACPI GPE0_BLK */
PIO_RANGE(0x820, 0x8),
/* Port I/O: e000-e0ff : 0000:07:00.0 */
PIO_RANGE(0xe000, 0x100),
/* Port I/O: f000-f0ff : 0000:04:00.0 */
PIO_RANGE(0xf000, 0x100),
//pio range for invalid pio read, port 414 size 1
PIO_RANGE(0x414, 0x1),
PIO_RANGE(0xb2, 0x2),
//serial 2
PIO_RANGE(0x2f8, 0x8),
},
.pci_devices = {
/* IVSHMEM: - net guest1*/
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.domain = 0x0,
.bdf = (0x0f << 3),
.bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
.num_msix_vectors = 2,
.shmem_regions_start = 0,
.shmem_dev_id = 0,
.shmem_peers = 2,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
},
/* PCIDevice: 00:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.domain = 0x0,
.bdf = 0x0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x9,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 11,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.3 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xb,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 11,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x10,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x18,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x19,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 11,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x20,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x38,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x39,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 11,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x40,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x41,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 11,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc1,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc2,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc4,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc5,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc6,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc7,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 01:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x100,
.bar_mask = {
0xffffc000, 0xffffffff, 0xfffff000,
0xfffff000, 0x00000000, 0x00000000,
},
.caps_start = 20,
.num_caps = 11,
.num_msi_vectors = 32,
.msi_64bits = 1,
.msi_maskable = 1,
.num_msix_vectors = 33,
.msix_region_size = 0x1000,
.msix_address = 0xfe902000,
},
/* PCIDevice: 02:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x200,
.bar_mask = {
0xffff8000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 31,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xfe6a2000,
},
/* PCIDevice: 02:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x201,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffe0000,
},
.caps_start = 39,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x202,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 43,
.num_caps = 5,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x300,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 48,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x308,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 48,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x320,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 48,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 04:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x400,
.bar_mask = {
0xffffff00, 0x00000000, 0xfffff000,
0xffffffff, 0xffffc000, 0xffffffff,
},
.caps_start = 55,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 4,
.msix_region_size = 0x1000,
.msix_address = 0xfe500000,
},
/* PCIDevice: 07:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x700,
.bar_mask = {
0xf0000000, 0xffffffff, 0xffe00000,
0xffffffff, 0xffffff00, 0xfffc0000,
},
.caps_start = 64,
.num_caps = 14,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 07:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x701,
.bar_mask = {
0xffffc000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 78,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 08:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x800,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 85,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 08:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x802,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 92,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xfe400000,
},
/* PCIDevice: 08:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x803,
.bar_mask = {
0xfff00000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 92,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xfe2fe000,
},
/* PCIDevice: 09:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x900,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 85,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 09:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x902,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffff000,
},
.caps_start = 100,
.num_caps = 8,
.num_msi_vectors = 16,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 09:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x903,
.bar_mask = {
0xffff8000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 108,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
},
.pci_caps = {
/* PCIDevice: 00:01.1 */
/* PCIDevice: 00:01.3 */
/* PCIDevice: 00:03.1 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 0x4,
.flags = 0,
},
{
.id = 0x23 | JAILHOUSE_PCI_EXT_CAP,
.start = 0x3c4,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 00:07.1 */
/* PCIDevice: 00:08.1 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 01:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x80,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x90,
.len = 0x18,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0xc0,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0xc,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PWR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x160,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x1b8,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x300,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x400,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x900,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 02:00.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0x68,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x300,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x400,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 02:00.1 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
/* PCIDevice: 02:00.2 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
/* PCIDevice: 03:00.0 */
/* PCIDevice: 03:01.0 */
/* PCIDevice: 03:04.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x400,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 04:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x70,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VC | JAILHOUSE_PCI_EXT_CAP,
.start = 0x140,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x160,
.len = 0xc,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x170,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x178,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 07:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_REBAR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ATS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2b0,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PRI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2c0,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PASID | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2d0,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x320,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ARI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x328,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 07:00.1 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ARI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x328,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 08:00.0 */
/* PCIDevice: 09:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 08:00.2 */
/* PCIDevice: 08:00.3 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xc0,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 09:00.2 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SATA,
.start = 0xd0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 09:00.3 */
{
.start = 0x42,
.len = 0x1,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for Linux inmate, 1 CPU, 74 MB RAM, ~1MB shmem, serial ports
*
* Copyright (c) Siemens AG, 2013-2015
*
* Authors:
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[7];
struct jailhouse_pci_device pci_devices[1];
struct jailhouse_pio pio_regions[1];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.architecture = JAILHOUSE_X86,
.name = "linux-x86-demo",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG |
JAILHOUSE_CELL_VIRTUAL_CONSOLE_ACTIVE,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_irqchips = 0,
.console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO
},
},
.cpus = {
0b11000,
},
.mem_regions = {
/* IVSHMEM shared memory regions (networking) */
JAILHOUSE_SHMEM_NET_REGIONS(0x61f00000, 1),
/* low RAM */
{
.phys_start = 0x42000000,
.virt_start = 0,
.size = 0x00100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE |
JAILHOUSE_MEM_LOADABLE,
},
/* communication region */
{
.virt_start = 0x00100000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
/* high RAM */
{
.phys_start = 0x42100000,
.virt_start = 0x00200000,
.size = 0x8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE |
JAILHOUSE_MEM_LOADABLE,
},
},
.pio_regions = {
/*Port I/O: serial 1 */
PIO_RANGE(0x3f8, 0x8),
},
.pci_devices = {
/* IVSHMEM: 00:0f.0 - net guest1*/
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.domain = 0x0,
.bdf = (0x0f << 3),
.bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
.num_msix_vectors = 2,
.shmem_regions_start = 0,
.shmem_dev_id = 1,
.shmem_peers = 2,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
},
},
};
