On 16 Sep 2008, at 21:49 , Rob Hamerling wrote: > As far as I can see all our Jallib issues with 2.4g are fixed, and I > have closed 'm (I think Eur can close also issue 23).
Hmm. (from b18f452.asm) > v_lata EQU 0x0f89 > v_trisa EQU 0x0f92 > [..] > ; 38 led_direction = output > bcf v_trisa, 0,v__access ; > pin_a0_direction, 0,v__access > ; 40 forever loop > l__l166 > ; 41 led = on > movlb 31 > bsf v_lata, 0,v__banked ; x19, > 0,v__banked TRISA is accessed via the access bank, and LATA is accessed via bank_31. How strange. There are only 15 banks in a PIC18xxxx. The BSR register has only 4 bits: > Only the four lower bits of the > BSR are implemented (BSR3:BSR0). The upper four > bits are unused; they will always read ë0í and cannot be > written to. The BSR can be loaded directly by using the > MOVLB instruction. So why write 5 bits to it? I'll wait for the LED to blink. Meanwhile, I'm busy trying to receive data. It doesn't work too well. --- ir EE van Andel [EMAIL PROTECTED] http://www.fiwihex.nl Fiwihex B.V. Wierdensestraat 74, NL7604BK Almelo, Netherlands tel+31-546-491106 fax+31-546-491107 --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/jallib?hl=en -~----------~----~----~----~------~----~------~--~---
