> When use the serial interface and differentiate the reset signal  using a
> series capacitor (like you did) understand that a +/-12V reset signal which
> may come from the serial line (in fact is +/-15V if you read the EIA232
> standard or even +/-25V if you refer to older 232 standard) will create a
> rising pulse of +12V and a falling pulse of -12V at the output of that
> capacitor (the pin connected with MCLR). Since MCLR has fortunately the
> negative clamping diode to GND inside the PIC, the negative pulse is limited
> at -0.45...-0.6V, but the positive pulse above VDD (where VDD is the supply
> voltage of PIC) still exist. So, it was just the hazard that you didn't
> killed the PIC with this reset circuit, because the MCLR accept higher
> voltages up to Vpp level. Newer PICs have Vpp  lower and lower. So a good
> reset will provide THE SAME logic level and THE SAME minimum reset pulse no
> matter which value has the power supply or the voltage on the serial line
> (which could be as low as +/-6V for a laptop, +/-10V for a desktop or +/-15V
> on a serial terminal).
>
> Vasile

Thanks for your feedback on this, I haven't had time to reply. You
must be referring to my schematic: 
http://www.borntechi.com/temp/ICSP_BOOTLOADER.JPG
with RT reset.

I see how the series cap on RT could give too high or too low of a
voltage for MCLR if I get the signal direct from the serial port.
However, I am using a MAX232 level converter. I put that capacitor
there so I can get a spike down to 0v to get the reset (because RT is
the inverse of what I want). It could still give me a positive spike
up to +10v, but MCLR accepts voltages up to +13v anyways, so I guess
I'm ok there. I don't think I will get any spike less then 0v since
the normal voltage is 5v (I do get a spike down to 0v).

I just made a new schematic: http://www.borntechi.com/temp/ICSP_BOOTLOADER2.JPG,
This new schematic should have sufficient 1ms reset during power up
via R6/C7

Does anyone see any dangerous issues with my new schematic?

Thanks,
Matt.

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