On Apr 2, 3:31 pm, mattschinkel <[email protected]> wrote: > Mike, I'm sure your the best a documentation since you have experience > with it. However, I feel that you have great skill with other things > (such as getting more processor types implemented). Maybe your skills > could be used better elsewhere for now?
I'm not the person for more processor types. I took a little look at Kyle's code. The only other processor than PIC (My only interest is 10/12/16 for less than 18pins and otherwise 18F, for more than 40 DIP the 18FxxJxx) is ARM Cortex M series (not even other ARMs). I'll get round to documentation on JAL first, as that is a starting point for a "next gen" JAL aka "Handy" for ARM generating thumb/thumb2 only. > > This multitasking thing sounds interesting, do you have any samples? > > Matt. Kind words... It will be in Catpad Project. I will be adding DTMF, CW, RTTY and PSK tone detection / demodulation / modulation via interrupt syncronised / partially driven task from the RTC interrupt using DSP. I have decided this is very feasible on the 18Fxxxx series at 48MHz as it has HW 8x8. I would use mix of my 16bit signed Fixed point integer and 8 bit arithmetic and some intermediate 32 bit fixed point integer. The highest DTMF tone is 1633Hz, lowest is 697. Thusly a sample rate of at least 3266Hz is needed for ADC. Convert at once to I & Q, then the sample rate can be reduced to 1/2. Then multiply I & Q input by 8 + 2 frequencies (or 1 to 8) using the variation PolarToCartesian function as Numerically controlled oscillator AND multiplier that takes I & Q instead of R as input. Output is decimated by IIR low pass filter combined with resampling to about 160Hz or 80Hz sample rate. The other two tones are to detect RTTY dual carriers of SSB, or a CW or PSK signal. Since we have I & Q we can demodulate the 160 or 80 samples per second PSK (original tone between 300Hz and 1650Hz approx). The ADC needs prefixed by a 350Hz to 1600 Hz approx bandpass opamp filter. Only initial stage of DSP at > 3266Hz. (Conversion to I & Q via hilbert) next stage > 1633Hz rest of DSP less than 160Hz rate. Possibly I can't do DTMF, RTTY, PSK, CW all at same time. 300bps packet is possible, as is maybe SSTV and WeFax perhaps. 9600baud packet would be less likely. I might need external ADC as the microchip built in one isn't good enough (on 16F anyway, maybe the 18F4550 / 18FxxJxx are better?). Ideally you want to start with 12 to 16 bits ADC, 16 bit fixed point Integer and reduce to 8 bits later at end stages... How much time is 16x16 with 32 bit result in JAL on 18F4550? Anyone know? I presume the compiler *DOES* use the 8x8 HW multiplier? -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
