on 18F4550
we have pragma target USBPLL F48MHZ there is no such pragma on the 18F67J50, Yet if you are using external crystal, PLL, and High speed USB, the pdf datasheets look very similar. I looked at the datasheet for clock setup on both PIC and the jal device files, and I could not figure what pragma target USBPLL F48MHZ is for, or if it's important why it's not on 18FxxJxx is it redundant (i'll test later) if you have pragma target PLLDIV P5 -- divide by 5 - 20MHZ_INPUT (crystal = Pn x 4) pragma target CPUDIV P2 -- OSC1_OSC2_SRC_1_96MHZ_PLL_SRC_2 (only option for HS_USB) pragma target OSC HS_PLL pragma target FCMEN DISABLED pragma target IESO DISABLED These seem to be the same for both CPU, though the register and bits to set CPUDIV ratio are different locations. -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
