Thanks! This worked for 48Mhz internal OSC. Would you be able to make a blink sample with this config? What should I set IESO and FCMEN to?
include 18f67j50 -- target PICmicro -- include chip pragma target clock 48_000_000 -- oscillator frequency -- configuration memory settings (fuses) pragma target WDT disabled -- no watchdog pragma target PLLDIV P2 -- divide by 5 - 20MHZ_INPUT pragma target CPUDIV P1 -- no cpu system clock divide pragma target OSC INTOSC_NOCLKOUT_PLL -- HS crystal or resonator OSCTUNE_PLLEN = 1 -- set 96mhz pll OSCCON_SCS = 0b00 _usec_delay(1_000) -- wait for OSC PLL to settle On Sep 27, 10:35 am, Rob Hamerling <[email protected]> wrote: > Hi Matt, > > On 10/09/27 15:06, mattschinkel wrote: > > > Thanks Rob, after much guessing values, I got it to work with serial. > > I hope it is an educated guess! I would agree with you that the > oscillator(s) are pretty complicated (to configure). But when you take > the time to read chapter 2 of the datasheet or study the schematics > (Figure 2-1) you should be able to select the proper settings (I'm > pretty sure I'm not over-estimating your intellectual capabilities). > Don't you have a suitable scope or frequency meter to measure the > resulting frequency? > > > I'll try USB soon. The device file is ok, sorry about that I must have > > misread something. How is the OSC is calculated with these working > > values? Why is there P1(no devide) on CPUDIV, when on 18F4550 it is > > P2(div 2)? > > The PLL module requires a 4 MHz input and produces 96 MHz output. So > when you want to use the PLL module you must reduce the actual > oscillator frequency to 4 MHz. > > In figure 2-1 you can see that the 18f4550 taps the CPU frequency > directly after the PLL module while the 18f6750 taps it after a [1:2] > divider. Since both processors can run up to 48MHz for the 18f4550 you > have 1:1 (P1), but for the 18f67j50 you'll 1:2 (P2). > > Don't ask me why all PICs are different! > > > Can I use Internal Oscillator for USB? What settings can I use? > > Yes, why not, see fig 2-1. > pragma fuse_def OSC INTOSC_NOCLKOUT_PLL > INTOSC gives 8 MHz, so PLLDIV should be P2 [1:2] > Maybe also needed: OSCCON_SCS = 0b00 > Rest is the same as for HS_PLL > > Note: I have not tested this! > > > include 18f67j50 -- target PICmicro > > -- include chip > > pragma target clock 48_000_000 -- oscillator frequency > > -- configuration memory settings (fuses) > > pragma target WDT disabled -- no watchdog > > pragma target PLLDIV P5 -- divide by 5 - 20MHZ_INPUT > > pragma target CPUDIV P1 -- no cpu system clock divide > > pragma target OSC HS_PLL -- HS crystal or resonator > > OSCTUNE_PLLEN = 1 -- set 96mhz pll > > _usec_delay(1_000) -- wait for OSC PLL to settle > > Seems OK to me (with a 20 MHz crystal/resonator!). > > But you might specify more config bits, esp. IESO and FCMEN. > > Regards, Rob. > > -- > R. Hamerling, Netherlands ---http://www.robh.nl -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
