Hi Kiste, (Oliver?) 2010/10/8 Oliver Seitz <[email protected]>: > > Yes, in the pata_hd case it is used once for every 16-bit-read. PATA-Standard > says that even slow HD drives (PIO mode 2) can give you 8.3MBytes a second. > That is one 16-bit-read every 230ns. Stretching this to a minimum of 1200ns > or so just to avoid a "smallest delay" procedure seems not reasonable to me. > > The theoretical possible read rate drops from over 8MByte/s to below > 2MByte/s. I think that's noticeable.
You stated that the top transfer rate until now is 320k/sec. That is 160k of 16-bit read every second or 6.1 us per read. Using 100ns delay in stead of 1 us saves 0.9 microsecond, which is 15% (and not 400). Anyway, I guess this is worth the effort and IMO a inline delay function would be the best solution. Especially since the function can't give you an accurate delay, just guarantee you a minimal one. And if I would implement it, it would be something as straight-forward as: _asm nop ; 100 ns at 40 MHz if (target_clock > 40000000) then _asm nop ; with the nop above, 100 ns at 80 MHz end if if (target_clock > 80000000) then _asm nop ; with the nop above, 100 ns at 120 MHz end if The resulting code should be just one, two or three nop's and it is easy to understand what's happening. Joep -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
