Hi Noel, issue 140 (http://code.google.com/p/jallib/issues/detail?id=140) was opened for this bug. I had time to have a look and propose a fix (update jallib sources to at least revision 2320). I've written unittests to check, so far it should be ok but real-life testing is mandatory, so I'm waiting for your feedback !
Cheers, Seb 2010/11/5 Sebastien Lelong <[email protected]> > Hi Noel, > > So, this is for me, indeed :) > > 2010/11/5 noel <[email protected]> > > >> adc_channels: >> -- ----------------------------------------- >> -- FIRST CASE: >> -- - PCFG bits exist, >> -- - analog are dependent from each other >> -- - Vref config is done via PCFG bits >> -- combination >> -- ----------------------------------------- >> this is not correct for the 18F4620, as Vref config is done using VCFG >> > > Indeed > > >> >> further down the code loads ADC_PCFG_MAP:- >> [...] >> >> based on the above if ADC_NCHANNEL is not equals to 0 (ie Vref >> channels required) then 0b_0 will be loaded into ADCON1_PCFG (which on >> the 18F4620 sets ALL anaologue channels on!) - ie ADC_PCFG_MAP values >> are not correct. >> > > It seems one_vref and two_vref bits (2nd and 3rd element of each 3-tuple) > are kind of blank due to the lack of VCFG bits consideration. > > I'll try to have a look. > > Cheers, > Seb > > -- Sébastien Lelong http://www.sirloon.net http://sirbot.org -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
