OK, let's try again... As of rev. 2331, configuration bits selection through
ADC_PCFG_MAP should now be fixed. I've updated unittests to illustrate/check
this.

Basically, when using PIC like 18f4620, only the first configuration of each
3-tuples elements is considered. Second and third config are usually used to
set Vref, but that's only valid when this is done through PCFG bits. For
18F4620, these 2nd/3rd configs were kind of empty, as PCFG bits don't drive
Vref.

Let me know !

Cheers,
Seb

2010/11/16 Sebastien Lelong <[email protected]>

> Ooops, I forgot this point about PCFG_MAP... I'll fix this !
>
> Cheers,
> Seb
>
> 2010/11/16 noel <[email protected]>
>
> Hi Seb,
>>
>> sorry to say it doesn't work - VCFG is now set correctly, but PCFG is
>> still being loaded with 0b_0000 (which turns on all AD channels).
>>
>> for each PIC there is something like:
>> const byte ADC_PCFG_MAP [42] = {0b_1111, 0b_0, 0b_0, 0b_1110, 0b_0,
>> 0b_0, 0b_1101, 0b_0, 0b_0, 0b_1100,....}
>>
>> then at bottom of this section:
>>       if ADC_NVREF == 0 then
>>         no_vref = ADC_PCFG_MAP[idx]
>>         ADCON1_PCFG = no_vref
>>      elsif ADC_NVREF == 1 then
>>         one_vref = ADC_PCFG_MAP[idx + 1]
>>         ADCON1_PCFG = one_vref
>>      elsif ADC_NVREF == 2 then
>>         two_vref = ADC_PCFG_MAP[idx + 2]
>>         ADCON1_PCFG = two_vref
>>       end if
>>
>> so if ADC_NVREF == 0 we get the correct value for PCFG, but otherwise
>> PCFG is loaded with 0b_0.
>> I think the problem lies with how you generate these ADC_PCFG_MAP
>> constants - the code mentions something about the file being generated
>> (what from?).
>>
>> Cheers,  Noel.
>>
>>
>> On Nov 13, 10:12 am, Sebastien Lelong <[email protected]>
>> wrote:
>> > Hi Noel,
>> >
>> > issue 140 (http://code.google.com/p/jallib/issues/detail?id=140) was
>> opened
>> > for this bug. I had time to have a look and propose a fix (update jallib
>> > sources to at least revision 2320). I've written unittests to check, so
>> far
>> > it should be ok but real-life testing is mandatory, so I'm waiting for
>> your
>> > feedback !
>> >
>> > Cheers,
>> > Seb
>> >
>> > 2010/11/5 Sebastien Lelong <[email protected]>
>> >
>> >
>> >
>> >
>> >
>> > > Hi Noel,
>> >
>> > > So, this is for me, indeed :)
>> >
>> > > 2010/11/5 noel <[email protected]>
>> >
>> > >> adc_channels:
>> > >> -- -----------------------------------------
>> > >> -- FIRST CASE:
>> > >> --  - PCFG bits exist,
>> > >> --  - analog are dependent from each other
>> > >> --  - Vref config is done via PCFG bits
>> > >> --    combination
>> > >> -- -----------------------------------------
>> > >> this is not correct for the 18F4620, as Vref config is done using
>> VCFG
>> >
>> > > Indeed
>> >
>> > >> further down the code loads ADC_PCFG_MAP:-
>> > >> [...]
>> >
>> > >> based on the above if ADC_NCHANNEL is not equals to 0 (ie Vref
>> > >> channels required) then 0b_0 will be loaded into ADCON1_PCFG (which
>> on
>> > >> the 18F4620 sets ALL anaologue channels on!) - ie ADC_PCFG_MAP values
>> > >> are not correct.
>> >
>> > > It seems one_vref and two_vref bits (2nd and 3rd element of each
>> 3-tuple)
>> > > are kind of blank due to the lack of VCFG bits consideration.
>> >
>> > > I'll try to have a look.
>> >
>> > > Cheers,
>> > > Seb
>> >
>> > --
>> > Sébastien Lelonghttp://www.sirloon.nethttp://sirbot.org- Hide quoted
>> text -
>> >
>> > - Show quoted text -
>>
>> --
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>>
>
>
> --
> Sébastien Lelong
> http://www.sirloon.net
> http://sirbot.org
>



-- 
Sébastien Lelong
http://www.sirloon.net
http://sirbot.org

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