Rob, I like your way of tricking the problem. :)
The final effect looks better, now indeed it detects the positive edge of
RDY_IN. Assuming the RDY_In is 20ms and RDY_OUT delay in the main loop is
say 1ms that can be correctly seen.
The IOC is almost the same of mine (which started as jal and ended as
assembler)
But if you need to precise control the RDY_OUT time, that seems impossible
in a long main loop which is also large jitter generator ( using the
USB_serial for instance) .
Imagine that RDY_IN varies between say 100us to 100ms and RDY_OUT must stay
high a precise time until user reset it. The RDY_OUT control has to be
moved in the ISR, but then no delay will be allowed to catch the rising
edge...an interrupt  timer delay must be implemented.
thanks for your help!

On Sun, Oct 3, 2021 at 3:45 PM Rob Hamerling <[email protected]> wrote:

>
> Hi Vasili,
>
> Follow up of my previous message ...
>
> On 03/10/2021 10.32, vsurducan wrote:
>
>
> On the other hand, if you set only the detection of the rising edge ( 
> IOCAP_IOCAP0
> = high,  IOCAN_IOCAN0 = low),  RDY_OUT stayed indefinitely on high even
> on RDY_IN a positive edge occured, which seems wrong.
>
> With only rising edge interrupts this is a possibility:
>
>
> procedure IOC() is
>     pragma interrupt
>     if INTCON_IOCIF & IOCAF_IOCAF0 then -- edge interrupt on RDY_IN
>         IOCAF = IOCAF & 0xFE            -- clear IOCAF0
>         pin_RDY_OUT = high              -- RDY_OUT high
>     end if
> end procedure
>
> forever loop
>     if pin_RDY_OUT then
>         delay_1ms(20)
>         pin_RDY_OUT = low
>     end if
> end loop
>
>
>
> --
> *Rob H*amerling, Vianen, NL
>
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