Re: [JAVA3D] Grafic card question

[Richard Smith - Systems Engineer - Melbourne]

FWIW modern processors are all superscalar and pipelined with internal
microarchitecture. Comparisons, loop increment/decrements, and branches
may all be executed concurrently as they typically involve different
functional units.

In the trivial case of a null loop body, a compiler can eliminate the loop
altogether. Nevertheless, coding it in assembler (I'm using SPARC assembler
because its what I'm familiar with):

    ba    test
    clr   %o0       ! a = 0
test:
    cmp   %o0,%i0   ! Compare
    blt,a test      ! Branch
    add   %o0,1,%o0 ! Increment, exploit branch delay slot

This loop can execute in 1 clock cycle per trip. [In a slightly more complex
loop with 7 instructions per trip, I got performance ranging from 3 to 11
cycles due to alignment of instructions in the instruction cache.]

Real code with a significant loop body would have many opportunities to
schedule loop overhead code along with the body.

As has been pointed out, memory access patterns are far more important.  One
other class of optimisation not discussed so far is modulo-scheduling, which can
further reduce the loop overhead relative to the loop body.  Avoiding inhibitors
to modulo-scheduling can be extremely important in HPC codes.

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