> Saku Ytti
> Sent: Tuesday, December 20, 2016 7:22 PM
>
> On 20 December 2016 at 18:42, <[email protected]> wrote:
>
> > Both CRS-X and NCS6k are powered by nPower X1e NPU.
> > And my understanding is that it's Homogeneous(Same PPE type) MPSoC
> i.e. Symmetric MultiProcessing (SMP), much like all the chips out there (used
> in ASR9k or MX and PTX, ...).
> > The difference I understand is in the instruction set that the PPE is
> > running.
> > And my guess is that threads on each PPE are using run to completion
> scheduling.
> > Let me know your thoughts please.
> >
> > And by pipeline with regards to NPU design I understand pipelining of
> arrays of PPEs where each array in the pipeline consists of PPEs dedicated to
> a specific function(parse search modify). -like in ASR9k.
>
> Current gen ASR9k, EZchip, is like Trio, ALU FP or Huawei Solar, many
> identical
> cores, fully programmable, essentially you're only limited by time in what you
> can do. Where as NCS5k/Arista/Jericho, PTX are ASIC/pipelines, with much
> more specialised hardware with lot less flexibility, but what they do do, they
> do far more efficiently, which means denser boxes are pragmatic.
> Roughly speaking pipeline/ASIC is great for core, DC, in Edge you often may
> require richer features offered by NPU designs, and density isn't that
> crucial.
>
With regards to raw processing speed comparison I don't think it matter that
much whether it's an SMP(single PPE completely processes the packet head) or
Pipeline (packet head is processed through a pipeline PPE stages -each
specialized for different function (different instructions set)).
I think what matters the most is how much data does the PPE get (size of packet
head that will be processed) and the amount of instructions in the set (#of
computations/lookups -and resulting memory accesses).
Obviously apart from clock-rate and number of threads for each PPE of course.
A good example is QFP(ASR1K) and QFA(CRS3),
Same SMP architecture, but QFP PPE gets whole packet bodies and executes a
massive instruction set on each resulting in very limited pps performance,
whereas QFA PPE gets only packet heads and executes limited instructions set
resulting in massive improvement of pps performance.
Another good example is the hyper-mode on MX PFE, by reducing the instruction
set that each PPE executes on every packet head it needs to process you gain
some extra pps performance.
What I'm trying to say is that it doesn't matter that much how are the PPEs
organized on the NPU chip (SMP, Pipeline or even SIMD architecture).
adam
Adam Vitkovsky
IP Engineer
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