https://bugs.kde.org/show_bug.cgi?id=360008
--- Comment #10 from Carl Love <[email protected]> --- Yes, there are typos in that comment which is causing confusion. > The comment tells there are 64 VSR registers of 64 bits. Should say 128-bits not 64 bits. > that 'however, these are not "real" floating point registers': is that > speaking about fp[0..31] Should say fp[32..63] > Finally, the last paragraph tells 'the 32 floating point registers (AKA > VSR[0] to VSR[31])' yea, the AKA confuses things. I removed "(AKA VSR[0] to VSR[31])" I also added a diagram that shows the register layout. Basically copied from the ISA document. That should help the reader to visualize the layout. > In the code that initialises low_offset and high_offset : for VG_BIGENDIAN, > the comment tells > that the 64-bits are stored as Little Endian. Are the values really stored as > little endian, even > on a big endian platform ? I think the comment confused things more then it should have. I was trying to describe where the 64-bit values were but I see how you interpreted it. The four 32-bit values are stored in little endian or big endian format no mixed/partial format. So, I changed the comment to state where the four 32-bit values map to the array indicies to remove the confusion. I will re-spin the patch, update it in this bugzilla and retest everything on the various platforms before committing the patch. Thanks for the help. -- You are receiving this mail because: You are watching all bug changes.
