Hello,
You need to set the 30th bit of CR0 register to disable the cache.
I've tried disabling the L1/L2/L3 cache in an intel processor as follows.
#include <linux/init.h>
#include <linux/module.h>
MODULE_LICENSE("Dual BSD/GPL");
static int hello_init(void)
{
printk(KERN_ALERT "Hello, world\n");
__asm__("push %rax\n\t"
"mov %cr0,%rax;\n\t"
"or $(1 << 30),%rax;\n\t"
"mov %rax,%cr0;\n\t"
"wbinvd\n\t"
"pop %rax"
);
return 0;
}
static void hello_exit(void)
{
printk(KERN_ALERT "Goodbye, cruel world\n");
__asm__("push %rax\n\t"
"mov %cr0,%rax;\n\t"
"and $~(1 << 30),%rax;\n\t"
"mov %rax,%cr0;\n\t"
"pop %rax"
);
}
module_init(hello_init);
module_exit(hello_exit);
When I try to remove this module, the system hangs! Any help?
In Intel software developers manual, it is mentioned that apart from the
above you need to disable MTRR. I did that using the following command:
echo "disable=00" >| /proc/mtrr
Now when I run some sample benchmarks they show a slowdown of almost 1000x!!
This is not reasonable since the max. The slowdown I was expecting is 200x
considering that it will take 200 cycles to read from DRAM.
Thanks,
Andev.
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