On Thu, Oct 21, 2010 at 4:23 PM, Sitsofe Wheeler <[email protected]> wrote:
>> Now when I run some sample benchmarks they show a slowdown of almost 1000x!! >> >> This is not reasonable since the max. The slowdown I was expecting is 200x >> considering that it will take 200 cycles to read from DRAM. > > Assuming the cache was completely disabled, won't the impact be > cumulative? E.g. imagine a memory read takes one cycle from cache and > 100 from main memory. If you read 5 instructions from cache that will > take 5 cycles. If you read 5 instructions from main memory that will be > 5*100 so 500 cycles. If it is 10 instructions then it is 10 vs 1000 and > so on... > > Are you searching for an improvement in determinism? Yes, if that was so, the slowdown is still 100x. In my test case, I removed all the entries from /proc/mtrr and also disabled L1/L2/L3 caches. When I run a benchmark which runs for 4 sec with cache, it takes almost 3000 secs without cache. I think I am messing up the /proc/mtrr file. Regards, Andev. -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to [email protected] Please read the FAQ at http://kernelnewbies.org/FAQ
