On Mon, Nov 28, 2022 at 07:31:48AM -0800, Breno Leitao wrote:
> Currently x86_spec_ctrl_base is read at boot time, and speculative bits
> are set if configs are enable, such as MSR[SPEC_CTRL_IBRS] is enabled if
> CONFIG_CPU_IBRS_ENTRY is configured. These MSR bits are not cleared if
> the mitigations are disabled.
>
> This is a problem when kexec-ing a kernel that has the mitigation
> disabled, from a kernel that has the mitigation enabled. In this case,
> the MSR bits are carried forward and not cleared at the boot of the new
> kernel. This might have some performance degradation that is hard to
> find.
>
> This problem does not happen if the machine is (hard) rebooted, because
> the bit will be cleared by default.
>
> Suggested-by: Pawan Gupta <[email protected]>
> Signed-off-by: Breno Leitao <[email protected]>
> ---
> arch/x86/include/asm/msr-index.h | 4 ++++
> arch/x86/kernel/cpu/bugs.c | 10 +++++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/msr-index.h
> b/arch/x86/include/asm/msr-index.h
> index 4a2af82553e4..22986a8f18bc 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -54,6 +54,10 @@
> #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
> #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
>
> +/* A mask for bits which the kernel toggles when controlling mitigations */
> +#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
> SPEC_CTRL_SSBD \
> + | SPEC_CTRL_RRSBA_DIS_S)
SPEC_CTRL_RRSBA_DIS_S is a disable bit and I presume it needs to stay enabled.
Only when spec_ctrl_disable_kernel_rrsba() runs. And I'd say perf-wise it
doesn't cost that much...
Pawan?
> +
> #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
> #define PRED_CMD_IBPB BIT(0) /* Indirect Branch
> Prediction Barrier */
>
> diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
> index 3e3230cccaa7..4030358216c8 100644
> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -137,8 +137,16 @@ void __init check_bugs(void)
> * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
> * init code as it is not enumerated and depends on the family.
> */
> - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
> + if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
> rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> + /*
> + * Previously running software, like kexec for example, may
> + * have some controls turned ON.
> + * Clear them and let the mitigations setup below set them
> + * based on configuration.
> + */
/*
* Previously running kernel (kexec), may have some controls
* turned ON. Clear them and let the mitigations setup below
* rediscover them based on configuration.
*/
There's no "previously running software, like kexec".
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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