On Sat, Apr 27, 2013 at 10:49:52AM +0200, jp charras wrote: > The first question I am thinking is: > Why a by layer constraints. > Why do not have only 2 min clearance values: one for outer layers, > one for inner layers.
This is one of the 'esoteric' feature I talked about in another message. Usually (i.e. in 99% of the board) I'd say you are correct. It's mostly a technological contraint for alignment during lamination. Or maybe for drilling (for example our fabricator has different clearance/annulus requirement for NPTH, since another set of tools is being used and so on: I set it in the per-pad clearance...not optimal but effective). However there are special stackup where this would be needed. Usually it's set during padstack definition but since pcbnew hasn't the padstack concept we have to define this as clearance. What we call clearance by the way is overlapping with the antipad concept (which is *very* important in multilayer boards). Some fabricators also like removal of pads in layers where there is no electrical pickup, other one need them for the plating processing... this is another feature that would be useful, by the way. So is different spoke width depending on expected current (this is too currently addressed by pad properties). Or even selectively untented vias (thermal vias). There are lot of application specific 'tricks' that with many cads are difficult or impossible do apply. One process where different layers would have different process clearance (*not* electrical clearance: electrical clearance is designed knowing potentials and stuff, process clearance is needed by technology limitations and board manufacturing yield) is with with metal cores or embedded distributed capacitance. Both of them are for somewhat specialized applications (high current and high frequency, respectively) but *could* be useful if not too difficult to implement. > Your answer was "use the more restrictive value". It's like the 'track width' rule: in fact there should be a minimum and a maximum width to check for a class. The minimum for fabrication purposes, the maximum for design correctness. True tale: I had some solenoid drivers with fuse protection and stuff. One section of track was reduced to 0,2mm (I wasn't probably aware that was one of *these* tracks). Guess what burns first with the output shorted :D > The best decision must be taken before creating/modifying dialogs, > the code and the file format. > Remember also the calculation time is a major constraint in DRC. Final DRC (i.e. the one you call from the dialog) could be slow. DRC when laying track shouldn't (I suppose I could wait, like, maximum one second to accept/reject the whole thing). > In some cases (namely for tracks having a specific impedance) you > should have to use the defined width. Right, another use for the min/max track limits. I hate impedance controlled routing, but it seems these days people like to move megahertzes instead of amperes :D Another thing while we're wishlisting for the drc: there should be a way (in the component) to specify that same-pin pads are actually tied together in the component (without having to tie them explicitly with 'copper'); this would cover two important cases: the tactile switch which can be often used to bridge the 'common' and the board stiffener/busbar which is actually a big piece of conductive metal (i.e. an 'external' trace part). At the moment the workaround is using a fake jumper layer (not exactly elegant). This would also fix the nuisance of having to tie together irregularly shaped pads. -- Lorenzo Marcantonio Logos Srl _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
