On 22.04.2016 15:23, Tomasz Wlostowski wrote: > IMHO it can be done without any changes on the eeschema side by adding a > special component to the standard library (just like GND/power ports).
Yes, but that'd feel like more of a hack. > PCBnew could interpret it as a zero-sized copper pad. Some DRC > modifications would be needed to correctly take into account clearances > of the nets connected by a tie. Well, the special pad (which I'd simply use the largest of the connected netclasses' width for) would be allowed to coincide with other pads and vias, modify zone fill around itself and even relax DRC rules, so this would be a *very* special component, so I'm not sure piggybacking it off component placement is going to do us any favours here. Simon
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