On Sun, Apr 24, 2016 at 01:48:22PM +0200, jp charras wrote: > Le 23/04/2016 00:50, Simon Richter a écrit : > > On 22.04.2016 15:23, Tomasz Wlostowski wrote: > > > >> IMHO it can be done without any changes on the eeschema side by adding a > >> special component to the standard library (just like GND/power ports). > > > > Yes, but that'd feel like more of a hack. > > > >> PCBnew could interpret it as a zero-sized copper pad. Some DRC > >> modifications would be needed to correctly take into account clearances > >> of the nets connected by a tie. > > > > Well, the special pad (which I'd simply use the largest of the connected > > netclasses' width for) would be allowed to coincide with other pads and > > vias, modify zone fill around itself and even relax DRC rules, so this > > would be a *very* special component, so I'm not sure piggybacking it off > > component placement is going to do us any favours here. > > > > Simon > > Have you a look at Altium, and how Altium handles net ties ? > > I know there are some bad ideas in Altium, but there are also some good and > very good ideas. > > - In schematic, it is a special component (not very special in fact, just a > component with an > attribute set), associated to a footprint, perfectly compatible with current > Eeschema files. > - On board, it is a special footprint , but not very special: it can be > currently made in Pcbnew, > with no (or minor changes) in code (perhaps just a enhancement in DRC). > > > Therefore, I don't think using a special component/special footprint is just > a hack: it could be the > right way to do.
+1 (for what is worth...) -- Marco Ciampa I know a joke about UDP, but you might not get it. ------------------------ GNU/Linux User #78271 FSFE fellow #364 ------------------------ _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
