Maybe a bit of further clarification will help.
We are talking about at least two different things here.
First issue is what i guess most of you have in mind. The thing about
mask clearance. Here the normal way is of course to enter the
restrictions of your board house globally into kicad.
But some very small and specialized components need extremely tight
requirements. If you select such a component you already know that your
manufacturer can produce with such tight requirements.
In most cases you don't want to have these tight requirements for all
components on the board as it will increase the price. So you create a
specialized footprint for this one component and don't want the global
settings to interfere with your design. All other components on the
board will use the global settings which allow for larger tolerances.
(will increase yield)
And then there is the second topic of the paste stencil.
The global settings here are less for ensuring correct alignment and
more for a global paste reduction. In most cases the manufacturer will
take care of this. (This is why the default in kicad is 0)
But if you have a component with a large "exposed pad" in the middle you
need to reduce paste on it in a controlled manner. Typically you aim for
about 65% paste coverage and hope for 50% coverage after soldering.
This paste also needs to be split up. One reason for this is to allow
gases to escape (better solder result). Another reason is such that the
squeegee dose not bend too much. (would result in uneven paste application)
If the pad also includes vias for thermal conductivity you might choose
to avoid the area around these vias with paste to reduce loss of paste.
(Otherwise you might need to tend or even better fill the vias. -> more
expensive)
In short: There are legitimate reasons why you might need tight control
over the paste and mask layer. Most users who use reflow soldering will
encounter some instance where they need to take control over the paste
layer. People who work with very small components might also need to
take control over the mask layer.
On 28/04/18 13:37, Strontium wrote:
On 28/04/18 18:51, jp charras wrote:
Le 28/04/2018 à 10:08, Eeli Kaikkonen a écrit :
It still looks to me that the original problem wasn't understood, and I wasn't
able to make it
clear. A Solder Mask Defined footprint means that the solder mask opening is
smaller than the
underlying copper area. It may also be differently shaped than the underlying
copper pad. Also the
paste area may be differently shaped than the copper or solder mask. In these
cases it should be
possible to define the mask and paste areas exactly, without adding or removing
anything. The
logical way of doing it, if KiCad had took it into consideration, would be to
draw the pad shape and
set the clearances to 0, and the pad would always keep the exact dimensions.
But now, because 0 is a
special case and means "add here some other value" the pad dimensions - we are
talking about
non-copper pads - will change unpredictably. This works for normal Non Solder
Mask Defined pads with
copper, but not for pads which are mask only or paste only.
The only possible solution ATM is to give very small clearance values so that
the original size of a
mask-only pad is for example 0.3x0.45mm and the efficient value will be
0.300001x0.450001mm. If the
clearances are left to 0 they can be anything, depending on the project's
values, and the footprint
doesn't work anymore. Remember that modern Solder Mask Defined footprints are
mostly very small and
tolerances are small. You can't add or remove 0.05mm without it going wrong.
I perfectly understood what you are saying.
But I do not agree with you.
but if "You can't add or remove 0.05mm without it going wrong" it means the
final board can be wrong.
Just because the solder mask opening areas can be not at the place you are
expecting, due to
registration issues.
I am thinking you are not taking in account this problem.
If you are thinking this problem does not exist, just set the solder mask
margin to 0
JP, I agree with you about solder mask registration issues in the normal
course, however there are components with specified footprints (like the
one Eeli linked to) that have very tight tolerances. Now, the fact that
those specifications exist means that it is possible (although it may be
expensive and not a normal process) to get registration of the solder
mask to meet or exceed the tolerances required of these footprints,
otherwise the footprint would not be defined this way.
Eeli is really talking about "features" of the footprint, and these
special "features" are modelled as a kind of pad, but are not really
pads. In this situation I can see that a way to "disable" the global
clearances from having any effect for a particular "feature" pad would
be desirable. Might be a useful thing for V6?
Steven
See for example http://www.ti.com/lit/ug/slra003d/slra003d.pdf
Eeli Kaikkonen
2018-04-28 10:28 GMT+03:00 jp charras <[email protected]
<mailto:[email protected]>>:
Some info about these masks:
For custom shaped pads, building a solder mask shape with a negative
margin can create issues
(unpredictable shape for non convex polygons).
So it is not allowed.
Margin in solder mask layers is needed because there are always
registration issues between the
copper layers and the solder mask layer.
Therefore, because the X and Y registration position error, you need a
actual mask size bigger than
the area defined by a pad, to be sure the actual solder mask does not
cover the pad (the hole in
mask always covers the pad area).
X/Y max error depends on your board house, so this is the reason to have
the registration tolerance
defined for the whole board (unless you know your board house, you cannot
reliably use a defined
tolerance: it could be too small or too large)
I am guessing there are also similar registration problems for the solder
mask, but I don't know
them.
--
Jean-Pierre CHARRAS
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