Please table this conversation until we start talking about the new constraint management system as part of v6 development. I don't really have time right now an I would rather not loose any valuable input. I will open up the discussion once we have an initial draft in place.
Cheers, Wayne On 1/14/19 5:31 PM, [email protected] wrote: > Hallo Wayne, > > Sorry for the repeat message, but I never managed to subscribe to the > mailing list using my usual e-mail account. > > I would be glad to elaborate on that. But the main point is that for > power electronics a net clearance is not all that usefull. The simplest > example is when you have a DC-DC converter which is supposed to have 4kV > isolation between input and output, but both the primary and secondary > circuits are 12V. > > Another example is a high voltage half bridge. You have for example the > 1kV and the 0V rail, and a switching node which is either 1kV or 0V. This > switching node has a gate driver attached to it which is low voltage (for > example 12V) within itself and needs only 0.2mm clearance. The gate driver > group of nets needs 3.2mm clearance from both the 1kV and 0V rail however. > > What Eagle does is that you can have 32 netclasses (I need more please > ;-) ). A clearance matrix gives the clearance between the netclasses > (and within the netclass itself on the diagonal), obviously this matrix > is symmetric. > > regards, > > Mark > > Wayne Stambaugh <[email protected]> wrote: > > Hey Mark, > > Will do. This will give us a chance to better understand how to even > map this over to KiCad. I'm still no sure I even understand what is > meant by netclass to netclass clearance. > > Cheers, > > Wayne > _______________________________________________ Mailing list: https://launchpad.net/~kicad-developers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-developers More help : https://help.launchpad.net/ListHelp
