I want to avoid exceptions as much as possible. Thus, I suggest we put all LGA, CGA and BGA at 0.5. Is QFN also at 0.15?
On Mon, Sep 15, 2014 at 9:35 AM, Lorenzo Marcantonio < [email protected]> wrote: > On Mon, Sep 15, 2014 at 08:41:16AM -0400, Carl Poirier wrote: > > > On another note, now that the courtyard is found in the module editor, I > > think it would be fair to add it to the convention. I personally would go > > for a 0.25mm clearance. Anyone objects? > > 0.25 clearance is the common IPC value for SMD component, measured from > the pad edges and then enlarged to enclose the silkscreen drawings. > > Except for LGA/BGA where is bigger to allow for reworking equipment. > > The complete table (for the nominal enviroment is): > - Aluminum cap 0.5 > - LGA/CGA/BGA 0.5 - 1.0 - 2.0 depending on ball size > - Chip 0.15 (simple R, L, C) > - DFN 0.15 > - SODFL, SOTFL 0.15 > - Other things 0.25 > > In short, the exception are flat leads and grid arrays; however if you > don't need an aggressive packing using 0.25 for chips ease *a lot* > reworking. Aluminum caps are big and 'springy' so they have special > arrangements anyway. > > > -- > Lorenzo Marcantonio > Logos Srl > > -- > Mailing list: https://launchpad.net/~kicad-lib-committers > Post to : [email protected] > Unsubscribe : https://launchpad.net/~kicad-lib-committers > More help : https://help.launchpad.net/ListHelp >
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