On Mon, Oct 13, 2014 at 11:14:48AM -0400, Carl Poirier wrote: > Just a quick question, is there any problem with the courtyard exceeding > the PCB edges? In this case, is the DRC supposed to fail? I'm thinking > about board edge connectors.
Uhm good question. I don't remember anything about the board in the standard. AFAIK the courtyard is meant as a 'intercomponent' space, so it shouldn't matter. I do RAST card edges in this way if it helps: (module "CARDEDGE-RAST25-3" placed (layer "F.Cu") (tedit 514EEA2A) (descr "Direct Mating RAST 2.5 edge - 3 pin") (attr virtual) (fp_text reference "CARDEDGE-RAST25-3" (at 0 0) (layer "F.SilkS") (effects (font (size 1.2 1.2) (thickness 0.12))) ) (fp_text value "CARDEDGE-RAST25-3" (at 0 0) (layer "F.SilkS") hide (effects (font (size 1.2 1.2) (thickness 0.12))) ) (fp_line (start 5.75 -8.55) (end 5.75 0) (layer "F.CrtYd") (width 0.01)) (fp_line (start 5.75 0) (end 5 0) (layer "F.CrtYd") (width 0.01)) (fp_line (start 5 0) (end 5 -2) (layer "F.CrtYd") (width 0.01)) (fp_line (start 5 -2) (end -5 -2) (layer "F.CrtYd") (width 0.01)) (fp_line (start -5 -2) (end -5 -8.55) (layer "F.CrtYd") (width 0.01)) (fp_line (start -5 -8.55) (end 5.75 -8.55) (layer "F.CrtYd") (width 0.01)) (fp_line (start 4.4 -4.8) (end 5.6 -4.2) (layer "F.SilkS") (width 0.12)) (fp_line (start 5.6 -4.2) (end 5.6 -5.4) (layer "F.SilkS") (width 0.12)) (fp_line (start 5.6 -5.4) (end 4.4 -4.8) (layer "F.SilkS") (width 0.12)) (fp_line (start -5 -2) (end -5 0) (layer "Edge.Cuts") (width 0.12)) (fp_line (start 5 -2) (end 5 0) (layer "Edge.Cuts") (width 0.12)) (fp_line (start 5 -2) (end -5 -2) (layer "Edge.Cuts") (width 0.12)) (pad "3" connect rect (at -2.5 -4.8) (size 1.7 4.6) (layers "*.Cu" "*.Mask")) (pad "2" connect rect (at 0 -4.8) (size 1.7 4.6) (layers "*.Cu" "*.Mask")) (pad "1" connect rect (at 2.5 -4.8) (size 1.7 4.6) (layers "*.Cu" "*.Mask")) (pad "1" thru_hole oval (at 2.5 -7.5) (size 1.7 2) (drill 0.8 (offset 0 0.2)) (layers "*.Cu" "*.Mask")) (pad "2" thru_hole oval (at 0 -7.5) (size 1.7 2) (drill 0.8 (offset 0 0.2)) (layers "*.Cu" "*.Mask")) (pad "3" thru_hole oval (at -2.5 -7.5) (size 1.7 2) (drill 0.8 (offset 0 0.2)) (layers "*.Cu" "*.Mask")) (pad "" connect rect (at 0 -4.8) (size 8 5.1) (layers "*.Mask")) ) -- Lorenzo Marcantonio Logos Srl -- Mailing list: https://launchpad.net/~kicad-lib-committers Post to : [email protected] Unsubscribe : https://launchpad.net/~kicad-lib-committers More help : https://help.launchpad.net/ListHelp
