--- In [email protected], "johnppeter" <[EMAIL PROTECTED]> wrote: > > For newbies, this is a good exercise in properly placing power pins, > within eeschema. Unfortunately, I see no follow-up to Simon's posting. > > Briefly stated, Simon placed two 'LS00 NAND gates in a nonsense > example circuit. The idea was to have one of these gates ("U1") > powered by the fixed VCC rail; the second NAND gate ("U2") was to > receive its power through switched power. Obviously, these two gates > must exist in separate packages. And U2's pin 14 should NOT be > connected to the VCC rail. > > But the 'LS00 part has automatic placement of power pins. And I don't > see how U2-pin 14 was ever severed from the rail. > > CAN ANYONE ADVISE ON HOW TO FORCIBLY SEVER U2-14 FROM VCC? (Without > messing with the library record of 'LS00?) Do I have to create > another part in the library, where pin 14 is open? > > I downloaded Simon's schematic, from his convenient link. Then I > generated a netlist from it, to see that his intuition was apparently > wrong. That is, in his schematic, Simon connected the power pin on U2 > to a distinct signal line in his schematic. According to the > resultant netlist, this did NOT sever U2 pin 14 from VCC. Instead, it > shorted the signal line to VCC. > > Could I be wrong? > Any comments welcome. > > > --- In [email protected], "mungewell" <mungewell@> wrote: > > > > Hi, > > I am seeing some weirdness in my netlist which is related to the use > > of invisible power pins, and I am just confussed on how these are > > supposed to behave. > > > > I have an area of a ciruit which I wish to power off, meaning that > > this will 'VCC' that will not be connected to the any other VCC. > > > > I was thinking that by making the power pins visible on the devices > > that connect to this switched supply and making a connection that this > > would break the connection to the other VCC. > > > > This does not seem to be the case. > > > > 1). Am I just mis-understanding how these connection work? > > > > 2). If so, is there another way to seperately power a component other > > than changing the part library to make these pins visible? > > > > > > I have put an example in: > > http://groups.yahoo.com/group/kicad-users/files/Mungewell/ > > > > The signal on P6/2 supposed to power U2. However in the netlist it is > > connected to P5/1 and U1/14 as well...... > > > > Strangly enough in my real board, the signal is actual shorted to GND > > rather than VCC - bizar! > > > > Simon. > > > Hi, In the schematic pin 14 of both U1 and U2 are connected to vcc AND P6/2. This is because pin vcc is set as common to all units in the symbol (which contains 4 units). In order to change this you need to create a new symbol in which pins 7 and 14 are not common to all 4 units.This is done in pin edit->pin properties->pin options of Libedit. Obviously in a real chip each gate can not be powered separately (single gate tiny logic chips can be used for this if needed) and 2 physical devices would have to be used if using a standard logic chip. I feel that allowing nets in EESchema to be highlighted (as in PCBNew) would help to show how this works.Lets hope it can be implemented one day. If I can help any further please ask.
David.
