Have you tried selecting "Vias on mask" on the Gerber plot dialog?
Regards, Robert. Berceanu Cristian wrote: > Hi, > I have been working with several PCB manufacturers who usually complain about > the vias being covered with solder resist (I believe "tented" is the correct > term). When I generate the gerbers from KiCAD, I can see that no openings for > the VIAs are operated in the solder mask, which means that basically the vias > are covered in solder mask (green stuff). > Is there an automated way to make solder mask openings around all the vias > in the design (I mean, a different way than doing it manually for every via, > with zones)? > > I am familiar with the "Mask Clearance" setting under the "Dimensions-> Traks > and vias" menu, but it does not seem to operate on vias. > > Thanks in advance, > Cristian > > > > > > > ------------------------------------------------------------------------ > > > No virus found in this incoming message. > Checked by AVG - www.avg.com > Version: 8.0.237 / Virus Database: 270.11.10/1996 - Release Date: 03/11/09 > 20:42:00 >
