Care to have a peek at my layout? I separated GND and DGND with R27 and created two zones for GND and two for DGND and separated them with a moat,
The really bad guys are obviously tehe FETs and the sense resistors, but I also expect some static from the MOS drivers (ICL7667) when they rush current into the gate capacitance. - Anders Gustafsson Engineer, CNE6, ASE Pedago, The Aaland Islands (N60 E20) www.pedago.fi phone +358 18 12060 mobile +358 40506 7099 fax +358 18 14060 >>> Robert <[email protected]> 2009-08-23 12:53 >>> ... I don't know if there is a better way (though a zero ohm link sounds like a cunning idea). Regards, Robert.
