From: "Bob La Quey" <[EMAIL PROTECTED]>
On 3/30/07, Andrew Lentvorski <[EMAIL PROTECTED]> wrote:
Bob La Quey wrote:
> Yeh. I have often wondered if VHDL and the other hardware
> modeling languages were not a better starting place for
> a general purpose programming language.
Given that I am currently teaching Verilog to CS students, I'm pretty
sure that suggestion is not a good idea. The constructs are too
low-level.
So do you have an alternative?
Or a higher level language you would suggest?
Or a vision of what such a language might be?
Criticism is easy. We can all be critiques. Do you have
a way forward?
A few problems with VHDL in my mind, having used it back in school.
1)Too based in hardware, variables in any real language are more than 0 or
1.
2)To do anything you need a state machine. Every CS student should
definitely learn state machines, but it shouldn't be the first thing they
learn.
3)Every instruction running simultaneously would be a mind fuck. They
wouldn't be able to handle it.
4)Too hard to program moderately difficult assignments.
5)Too many concepts non-existent. No loops, no arrays, etc.
Personally, I like C as a learning language. It has pretty much everything
they'll need to know, won't allow them to fall into the giant class library
trap, and teaches them pointers and memory management early. And for those
who claim the last is a bad thing- if they can't figure out a simple
request, use, release sequence, they shouldn't ever touch a compiler again.
Gabe
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