On 3/30/07, Gabriel Sechan <[EMAIL PROTECTED]> wrote:
>From: "Bob La Quey" <[EMAIL PROTECTED]> >On 3/30/07, Andrew Lentvorski <[EMAIL PROTECTED]> wrote: >>Bob La Quey wrote: >> > Yeh. I have often wondered if VHDL and the other hardware >> > modeling languages were not a better starting place for >> > a general purpose programming language. >> >>Given that I am currently teaching Verilog to CS students, I'm pretty >>sure that suggestion is not a good idea. The constructs are too >>low-level. > >So do you have an alternative? > >Or a higher level language you would suggest? > >Or a vision of what such a language might be? > >Criticism is easy. We can all be critiques. Do you have >a way forward? > A few problems with VHDL in my mind, having used it back in school. 1)Too based in hardware, variables in any real language are more than 0 or 1. 2)To do anything you need a state machine. Every CS student should definitely learn state machines, but it shouldn't be the first thing they learn. 3)Every instruction running simultaneously would be a mind fuck. They wouldn't be able to handle it. 4)Too hard to program moderately difficult assignments. 5)Too many concepts non-existent. No loops, no arrays, etc. Personally, I like C as a learning language. It has pretty much everything they'll need to know, won't allow them to fall into the giant class library trap, and teaches them pointers and memory management early. And for those who claim the last is a bad thing- if they can't figure out a simple request, use, release sequence, they shouldn't ever touch a compiler again. Gabe
Sigh, why can I not get you guys to generalize. I suppose it is my fault for not communicating that intent. I like C ... but it teaches nothing about concurrency. I started off as a hardware guy. Then became a physicist, only later coming back to software. The essence of physics is abstraction. So often I am trying to suggest a more abstract version of the immediate model. So not VHDL specifically but the underlying abstractions, i.e concurrent machines, is what I mean. My point is not VHDL but the fact that hardware and hence hardware modeling languages are by their very nature concurrent as is most of reality. Reality consist of many machines doing all kinds of things concurrently. I don't know much about this but I suspect that the "language of the future" needs to have concurrency built in at its lowest level and may look more like a hardware modeling language than like a conventional programing language, i.e more like a very high level layer on Verilog or VHDL than likie C, Pascal or Java. It depends how yo think about problem solution. I have always thought about solving problems by building machines. Often I use a language like C simply as a tool to implement some problem solving machine. A language that made the implementation of concurrent machines more natural might grow from hardware modeling languages rather than conventional programming languages. BobLQ -- [email protected] http://www.kernel-panic.org/cgi-bin/mailman/listinfo/kplug-lpsg
