* Gregory Haskins <[EMAIL PROTECTED]> wrote:
> > pci is level triggered, so maybe the guests just handle the
> > inaccuracy.
> >
>
> Good point. I'm not sure how this works today. Perhaps we just get
> lucky that nothing checks the IRR in the IOAPIC coupled with a bug in
> the IOAPIC model that an APIC message is sent out even if the
> interrupt is not acknowledged. It would explain why it works today,
> anyway. Either way, I would like to get this modeled "right" this
> go-round, so the point is moot.
on real hardware, some devices produce edges, some devices produce level
signals that need to be deasserted. The basic model of a PIC is that it
has 'pins', which convert the signal arriving on those pins into
interrupts. Qemu itself should only know about the pin enumeration, and
should only be able to raise/lower the (virtual) 'signal' on such a pin.
PCI can be level and edge triggered too, and IO-APICs can be programmed
on a per-pin basis to detect edge-high, edge-low, level-high, level-low
signals.
there is a remote possibility that some OSs depend on certain devices
being level-triggered: for example if you get an IRQ from a
level-triggered device and _dont_ deassert that signal from the IRQ
handler (intentionally so), then the semantics of current hardware will
cause a second interrupt to be sent by the PIC, after the APIC message
has been EOI-ed in the local APIC. While such "repeat interrupts" would
be pure madness to rely on i think, i'm not sure it's not being done.
Note that if the same IO-APIC pin is set up to detect edges then not
deasserting the signal would not cause a 'repeat interrupt'. Whether
such accurate emulation of signalling is needed depends on the hardware
semantics of the devices we emulate.
Ingo
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