* Gregory Haskins <[EMAIL PROTECTED]> wrote:
> Hi all,
>
> Attached is a snapshot of my current efforts on the kernel side for
> the in-kernel APIC work. Feedback welcome.
good work and nice patch! :)
> My current thoughts are that we at least move the IOAPIC into the
> kernel as well. [...]
yes. And then do the final 10% move of handling the i8529A in KVM too.
That would mean that PV drivers could inject IRQ events without having
to schedule back to qemu. Especially if the IRQ is masked this avoids a
context-switch. (with any PIC component in qemu we have no choice but to
always wake up qemu and let it handle the event - even if it results in
a 'no vector generated' decision). This is a plus because most PV
drivers will do IO completion from irq context and possibly on other
CPUs.
> The current Bochs/QEMU system model paints a fairly simple ISA
> architecture utilizing a single IOAPIC + dual 8259 setup. Do we
> expect in-kernel injected IRQs to follow the ISA model (e.g. either
> legacy or PCI interrupts only limited to IRQ0-15) or do we want to
> expand on this? [...]
yes, we should probably expand them - it's not hard. PV/accel drivers
would most likely hook up to free pins to unshare the interrupts.
> If the latter, we also need to decide what the resource conveyance
> model and vector allocation policy should be. For instance, do we
> publish said resources formally in the MP/ACPI tables in Bochs? Doing
> so would allow MP/ACPI compliant OSs like linux to naturally route the
> IRQ. Conversely, do we do something more direct just like we do for
> KVM discovery via wrmsr?
for PV/accel drivers we dont need any extra ACPI enumeration - the
hypercall API is good enough to connect to the hypervisor, and i suspect
all guest OSs we care about allow drivers to allocate an IRQ vector for
a new device, without having that device enumerated in ACPI.
Ingo
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