Hi Avi,
Attached is a patch to implement instruction:
push reg (opcode 0x50 - 0x57)
Please apply or comment.
--
Thanks & Regards,
Nitin
Open Source Technology Center, Intel Corporation
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commit 7f712b2d8cda67299e17473356050490a5c05be5 Author: Nitin A Kamble <[EMAIL PROTECTED]> Date: Thu Aug 16 19:47:19 2007 -0700
Implementing emulation of instructions:
push reg (opcode 0x50-0x57)
Signed-off-by: Nitin A Kamble <[EMAIL PROTECTED]>
diff --git a/drivers/kvm/x86_emulate.c b/drivers/kvm/x86_emulate.c
index cfdbaa5..09ca692 100644
--- a/drivers/kvm/x86_emulate.c
+++ b/drivers/kvm/x86_emulate.c
@@ -99,7 +99,8 @@ static u8 opcode_table[256] = {
/* 0x40 - 0x4F */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/* 0x50 - 0x57 */
- 0, 0, 0, 0, 0, 0, 0, 0,
+ ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
+ ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
/* 0x58 - 0x5F */
ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
@@ -1247,7 +1248,21 @@ pop_instruction:
register_address_increment(_regs[VCPU_REGS_RSP], op_bytes);
no_wb = 1; /* Disable writeback. */
break;
+ case 0x50 ... 0x57: /* push reg */
+ if (op_bytes == 2)
+ src.val = (u16) _regs[b & 0x7];
+ else
+ src.val = (u32) _regs[b & 0x7];
+ dst.type = OP_MEM;
+ dst.bytes = op_bytes;
+ dst.val = src.val;
+ register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
+ dst.ptr = (void *) register_address(
+ ctxt->ss_base, _regs[VCPU_REGS_RSP]);
+ d |= Mov; /* force writeback */
+ break;
}
+
goto writeback;
twobyte_insn:
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