On Tue, 2007-10-30 at 18:06 -0700, Avi Kivity wrote:
> Nitin A Kamble wrote:
> > Hi Avi,
> > Attached is the patch to implement emulation of instructions
> > mov rl, imm8 (opcodes 0xb0-0xb3)
> > mov rh, imm8 (opcodes 0xb4-0xb7)
> > mov r, imm (opcodes0xb8-0xbf)
> >
> >
> > @@ -146,8 +146,12 @@ static u16 opcode_table[256] = {
> > 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
> > ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
> > ByteOp | ImplicitOps, ImplicitOps,
> > - /* 0xB0 - 0xBF */
> > - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> > + /* 0xB0 - 0xB7 */
> > + Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
> > SrcImmByte,
> > + Mov | SrcImmByte, Mov | SrcImmByte, Mov | SrcImmByte, Mov |
> > SrcImmByte,
> > + /* 0xB8 - 0xBF */
> > + Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
> > + Mov | SrcImm, Mov | SrcImm, Mov | SrcImm, Mov | SrcImm,
> > /* 0xC0 - 0xC7 */
>
> Perhaps adding DstReg would reduce the decoding code later on?Avi, The decoding of register is significantly different for these instructions. It will be just moving code from one place to other place. + c->dst.ptr = + (unsigned long *)&c->regs[VCPU_REGS_RAX + (c->b & 0x3)]; + c->dst.ptr = + ((void *)&c->regs[VCPU_REGS_RAX + (c->b & 0x3)] + 1); + c->dst.ptr = + (unsigned long *)&c->regs[VCPU_REGS_RAX + (c->b & 0x7)]; > -- > Any sufficiently difficult bug is indistinguishable from a feature. > > -- Thanks & Regards, Nitin Open Source Technology Center, Intel Corporation ----------------------------------------------------------------- The mind is like a parachute; it works much better when it's open
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