Alexander Graf <[email protected]> writes:

> When running on a POWER8 host, we get away with running the guest as POWER7
> and nothing falls apart.
>
> However, when we start exposing POWER8 as guest CPU, guests will start using
> new abilities on POWER8 which we need to handle.
>
> This patch set does a minimalistic approach to implementing those bits to
> make guests happy enough to run.
>
>
> Alex
>
> Alexander Graf (6):
>   KVM: PPC: Book3S PR: Ignore PMU SPRs
>   KVM: PPC: Book3S PR: Emulate TIR register
>   KVM: PPC: Book3S PR: Handle Facility interrupt and FSCR
>   KVM: PPC: Book3S PR: Expose TAR facility to guest
>   KVM: PPC: Book3S PR: Expose EBB registers
>   KVM: PPC: Book3S PR: Expose TM registers
>
>  arch/powerpc/include/asm/kvm_asm.h        | 18 ++++---
>  arch/powerpc/include/asm/kvm_book3s_asm.h |  2 +
>  arch/powerpc/include/asm/kvm_host.h       |  3 ++
>  arch/powerpc/kernel/asm-offsets.c         |  3 ++
>  arch/powerpc/kvm/book3s.c                 | 34 +++++++++++++
>  arch/powerpc/kvm/book3s_emulate.c         | 53 ++++++++++++++++++++
>  arch/powerpc/kvm/book3s_hv.c              | 30 -----------
>  arch/powerpc/kvm/book3s_pr.c              | 82 
> +++++++++++++++++++++++++++++++
>  arch/powerpc/kvm/book3s_segment.S         | 25 ++++++++++
>  9 files changed, 212 insertions(+), 38 deletions(-)
>

I did most of this as part of 

[RFC PATCH 01/10] KVM: PPC: BOOK3S: PR: Add POWER8 support
http://mid.gmane.org/[email protected]

Any reason why that is not picked up ? TM was the reason I didn't push the
patchset again. I was not sure how to get all the TM details to
work.

-aneesh

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