Yang, Sheng wrote:
I think we should do a little more than just write msr to update mtrr.
Intel SDM 10.11.8 "MTRR consideration in MP Systems" define the procedure to
modify MTRR msr in MP. Especially, step 4 enter no-fill cache mode(set CR0.CD
bit and clean NW bit), step 12 re-enabled the caching(clear this two bits).
We based on these behaviors to detect MTRR update.
Why not simply flush the mmu on an mtrr write?
(though of course I have no objection to doing what the manual says)
--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
