Sorry there was a type,
The question is:
How is VFIO restricting software from writing to MSI/MSI-X vectors
of the device.
-----Original Message-----
From: Chalamarla, Tirumalesh
Sent: Thursday, June 26, 2014 11:16 AM
To: Chalamarla, Tirumalesh; Joerg Roedel; Will Deacon
Cc: [email protected]; open list; [email protected];
[email protected]; [email protected];
[email protected]; [email protected]; moderated list:ARM
SMMU DRIVER
Subject: RE: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
IOMMU_CAP_INTR_REMAP
When I say emulating ITS, I mean translating guest ITS commands to physical ITS
commands and placing them in physical queue.
Regards,
Tirumalesh.
-----Original Message-----
From: [email protected]
[mailto:[email protected]] On Behalf Of Chalamarla,
Tirumalesh
Sent: Thursday, June 26, 2014 11:08 AM
To: Joerg Roedel; Will Deacon
Cc: [email protected]; open list; [email protected];
[email protected]; [email protected];
[email protected]; [email protected]; moderated list:ARM
SMMU DRIVER
Subject: RE: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
IOMMU_CAP_INTR_REMAP
Forgive me if this discussion is not relative here, but I thought it is.
How is VFIO restricting devices from writing to MSI/MSI-X, Is all the vector
area is mapped by VFIO to trap the accesses. I am asking this because we might
need to emulate ITS somewhere either in KVM or VFIO to provide direct access to
devices.
And I don't see any mentions on that. I think this flag needs to be set by
ITS emulation.
Regards,
Tirumalesh.
-----Original Message-----
From: [email protected]
[mailto:[email protected]] On Behalf Of Joerg Roedel
Sent: Monday, June 16, 2014 8:39 AM
To: Will Deacon
Cc: [email protected]; [email protected]; open list;
[email protected]; [email protected]; moderated
list:ARM SMMU DRIVER; [email protected];
[email protected]; Christoffer Dall
Subject: Re: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
IOMMU_CAP_INTR_REMAP
On Mon, Jun 16, 2014 at 04:25:26PM +0100, Will Deacon wrote:
> Ok, thanks. In which case, I think this is really a combined property
> of the SMMU and the interrupt controller, so we might need some extra
> code so that the SMMU can check that the interrupt controller for the
> device is also capable of interrupt remapping.
Right, that this is part of IOMMU code has more or less historic reasons on
x86. Interrupt remapping is purely implemented in the IOMMU there, so on ARM
some clue-code between interrupt controler and smmu is needed.
Joerg
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