Thanks for the clarification Alex, That’s exactly my point, why are we relying
on QEMU or something else to emulate the MSI space when we can directly give
access to devices using ITS (of course with a small emulation code).
This way we are also benefited from all ITS services like VCPU migration etc.
What about non QEMU VFIO users, for example, if I wanted to use VFIO to assign
a device to a user process I don't need to depend on QEMU. I thought this is
one of the main goals of vfio to make it independent of hypervisors.
Thanks,
Tirumalesh.
-----Original Message-----
From: Alex Williamson [mailto:[email protected]]
Sent: Thursday, June 26, 2014 12:00 PM
To: Chalamarla, Tirumalesh
Cc: Joerg Roedel; Will Deacon; [email protected]; open list;
[email protected]; [email protected];
[email protected]; [email protected]; moderated list:ARM
SMMU DRIVER
Subject: Re: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
IOMMU_CAP_INTR_REMAP
On Thu, 2014-06-26 at 18:41 +0000, Chalamarla, Tirumalesh wrote:
> Sorry there was a type,
>
> The question is:
>
> How is VFIO restricting software from writing to MSI/MSI-X
> vectors of the device.
All interrupts are configured via ioctl, not MSI config space or the MSI-X
vector table in MMIO space. VFIO protects the MSI config area by virtualizing
it (you can't actually write the physical enable bit or address/data through
VFIO). The MSI-X vector table is protected by preventing read, write, or mmap
access to it. QEMU provides further virtualization above the basics provided
by VFIO. We really can't guarantee that devices don't have backdoors to
configure these though.
See the realtek quirk in QEMU for an example of a device that has such a
backdoor. That's why we require interrupt remapping, so that a device that
does this can only hurt the guest, and require the user to opt-out if they feel
they have a sufficiently trusted guest. Thanks,
Alex
>
> -----Original Message-----
> From: Chalamarla, Tirumalesh
> Sent: Thursday, June 26, 2014 11:16 AM
> To: Chalamarla, Tirumalesh; Joerg Roedel; Will Deacon
> Cc: [email protected]; open list; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; moderated
> list:ARM SMMU DRIVER
> Subject: RE: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
> IOMMU_CAP_INTR_REMAP
>
> When I say emulating ITS, I mean translating guest ITS commands to physical
> ITS commands and placing them in physical queue.
>
> Regards,
> Tirumalesh.
>
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf Of Chalamarla,
> Tirumalesh
> Sent: Thursday, June 26, 2014 11:08 AM
> To: Joerg Roedel; Will Deacon
> Cc: [email protected]; open list; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; moderated
> list:ARM SMMU DRIVER
> Subject: RE: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
> IOMMU_CAP_INTR_REMAP
>
> Forgive me if this discussion is not relative here, but I thought it is.
>
> How is VFIO restricting devices from writing to MSI/MSI-X, Is all the vector
> area is mapped by VFIO to trap the accesses. I am asking this because we
> might need to emulate ITS somewhere either in KVM or VFIO to provide direct
> access to devices.
> And I don't see any mentions on that. I think this flag needs to be set by
> ITS emulation.
>
> Regards,
> Tirumalesh.
>
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf Of Joerg
> Roedel
> Sent: Monday, June 16, 2014 8:39 AM
> To: Will Deacon
> Cc: [email protected]; [email protected]; open list;
> [email protected]; [email protected];
> moderated list:ARM SMMU DRIVER; [email protected];
> [email protected]; Christoffer Dall
> Subject: Re: [RFC PATCH v6 04/20] iommu/arm-smmu: add capability
> IOMMU_CAP_INTR_REMAP
>
> On Mon, Jun 16, 2014 at 04:25:26PM +0100, Will Deacon wrote:
> > Ok, thanks. In which case, I think this is really a combined
> > property of the SMMU and the interrupt controller, so we might need
> > some extra code so that the SMMU can check that the interrupt
> > controller for the device is also capable of interrupt remapping.
>
> Right, that this is part of IOMMU code has more or less historic reasons on
> x86. Interrupt remapping is purely implemented in the IOMMU there, so on ARM
> some clue-code between interrupt controler and smmu is needed.
>
>
> Joerg
>
>
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