----- Original Message ----- > > > ----- Original Message ----- > > Il 16/09/2014 14:43, Andrew Jones ha scritto: > > > I don't think we need to worry about this case. AFAIU, enabling the > > > caches for a particular cpu shouldn't require any synchronization. > > > So we should be able to do > > > > > > enable caches > > > spin_lock > > > start other processors > > > spin_unlock > > > > Ok, I'll test and apply your patch then. > > Actually, yeah, please apply now in order to get A7 boards working. > I'll do a follow-on patch to fix the case above (which will require > deciding how to hand per cpu data).
Post coffee, I don't see why I shouldn't just use SCTLR.C as my boolean, which is of course per cpu, and means the same thing, i.e. caches enabled or not. I'll send a v2 that drops mem_caches_enabled, and modifies the logic of the spin_lock asm. drew > > drew > > > > > Once you change the code to enable caches, please consider hanging on > > spin_lock with caches disabled. > > > > Paolo > > -- > > To unsubscribe from this list: send the line "unsubscribe kvm" in > > the body of a message to [email protected] > > More majordomo info at http://vger.kernel.org/majordomo-info.html > > > _______________________________________________ > kvmarm mailing list > [email protected] > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm > -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
