On 20/04/2015 19:25, Jan Kiszka wrote:
> When hardware supports the g_pat VMCB field, we can use it for emulating
> the PAT configuration that the guest configures by writing to the
> corresponding MSR.
>
> Signed-off-by: Jan Kiszka <[email protected]>
I'm not sure about this. The problem is that, unlike Intel, AMD has no
way for the host to force its PAT value and ignore the guest's. I'm
worried about potential performance problems in the guest.
This is not as bad as on ARM, because the guest cannot disable the cache
snooping protocol and thus cache coherency is guaranteed (see tables
7-10 and 15-20 in the AMD docs), but still I think I'd prefer having
some knob (module parameter) to enable/disable gPAT. It's okay to make
it enabled by default.
Paolo
> ---
>
> Changes in v2:
> - add mark_dirty as found missing by Radim
>
> arch/x86/kvm/svm.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index ce741b8..68fdddc 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -3245,6 +3245,16 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct
> msr_data *msr)
> case MSR_VM_IGNNE:
> vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n",
> ecx, data);
> break;
> + case MSR_IA32_CR_PAT:
> + if (npt_enabled) {
> + if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
> + return 1;
> + svm->vmcb->save.g_pat = data;
> + mark_dirty(svm->vmcb, VMCB_NPT);
> + vcpu->arch.pat = data;
> + break;
> + }
> + /* fall through */
> default:
> return kvm_set_msr_common(vcpu, msr);
> }
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