On 20/04/2015 20:41, Jan Kiszka wrote:
> If the guest pushes data for DMA into RAM, it may assume that it lands
> there directly, without the need for explicit flushes, because it has
> caching disabled - no?
Yes, but Intel IOMMUs can have snooping control and in this case you can
just set memory to WB.
On Intel, KVM trusts the guest's PAT if the IOMMU is in use, and you do
not have an Intel IOMMU with snooping control. In this case
kvm_arch_has_noncoherent_dma(vcpu->kvm) returns true.
The same should work for AMD, so you can set the gPAT:
- to the guest's value if kvm_arch_has_noncoherent_dma(vcpu->kvm), and
then you return cachemode2protval(kvm_get_guest_memory_type(...)) from
svm_get_mt_mask to layer the guest MTRRs on top of the guest PAT.
- otherwise, to all WB (0x0606060606060606), and then you can return
either 0 or _PAGE_NOCACHE from svm_get_mt_mask to achieve either UC (for
MMIO regions) or WB (for everything else).
To sum up you have:
IOMMU? no IOMMU?
guest PAT obeyed ignored (all WB)
guest MTRR obeyed (svm_get_mt_mask) ignored (UC if MMIO, else WB)
host PAT always ignored always ignored
host MTRR always obeyed always obeyed
I think that kvm_arch_has_noncoherent_dma() can be resampled, and gPAT
updated, in wbinvd_interception.
Paolo
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