On 07/25/2011 08:28 AM, Avi Kivity wrote:
On 07/25/2011 04:17 PM, Gleb Natapov wrote:
On Mon, Jul 25, 2011 at 04:14:45PM +0300, Avi Kivity wrote:
> On 07/25/2011 04:07 PM, Anthony Liguori wrote:
> >On 07/20/2011 11:50 AM, Avi Kivity wrote:
> >>The current implementation of PAM and the PCI holes is broken in
several
> >>ways:
> >>
> >> - PCI BARs are not restricted to the PCI hole (a BAR may hide
memory)
> >
> >Technically, a BAR can be mapped to any non-RAM memory location.
>
> I understood TOM (Top Of Memory) to be fixed - can't find a register
> for it - but maybe I misread the spec.
>
PIIX3 spec:
2.2.11. TOM—TOP OF MEMORY REGISTER (Function 0)
Address Offset: 69h
Default Value: 02h
Attribute: Read/Write
What's it doing in PIIX3? Is it the same TOM?
This is a programmable register used to indicate the TOM for the
purposes of forwarding ISA DMA transactions.
It is unrelated to the I440FX notion of top of memory.
Regards,
Anthony Liguori
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