On Mon, 20 May 2013, Sanjay Lal wrote: > (1) Newer versions of the MIPS architecture define scratch registers for > just this purpose, but since we have to support standard MIPS32R2 > processors, we use the DDataLo Register (CP0 Register 28, Select 3) as a > scratch register to save k0 and save k1 @ a known offset from EBASE.
That's rather risky as the implementation of this register (and its presence in the first place) is processor-specific. Do you maintain a list of PRId values the use of this register is safe with? Maciej -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
