On Tue, Oct 10, 2017 at 07:38:27PM +0100, Dave P Martin wrote: > To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be > disabled. To take maximum advantage of the hardware, the full > available vector length also needs to be enabled for EL1 by > programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as > required, but this cannot override the limit set by ZCR_EL2.) > > Traps from EL0 to EL1 are also left enabled by virtue of setting > the relevant CPACR bit at its default (RES0) value. > > This patch makes the appropriate changes to the primary and > secondary CPU initialisation code. > > Signed-off-by: Dave Martin <dave.mar...@arm.com> > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Catalin Marinas <catalin.mari...@arm.com> _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
