The gicv{2,3}-active test sends an IPI from the boot CPU to itself, then
checks that the interrupt has been received as expected. There is no need
to use inter-processor memory synchronization primitives on code that runs
on the same CPU, so remove the unneeded memory barriers.Reviewed-by: Eric Auger <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Signed-off-by: Alexandru Elisei <[email protected]> --- arm/gic.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index e2e053aeb823..8bb804abf34d 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -367,6 +367,7 @@ static struct gic gicv3 = { }, }; +/* Runs on the same CPU as the sender, no need for memory synchronization */ static void ipi_clear_active_handler(struct pt_regs *regs __unused) { u32 irqstat = gic_read_iar(); @@ -383,13 +384,10 @@ static void ipi_clear_active_handler(struct pt_regs *regs __unused) writel(val, base + GICD_ICACTIVER); - smp_rmb(); /* pairs with wmb in stats_reset */ ++acked[smp_processor_id()]; check_irqnr(irqnr); - smp_wmb(); /* pairs with rmb in check_acked */ } else { ++spurious[smp_processor_id()]; - smp_wmb(); } } -- 2.30.1 _______________________________________________ kvmarm mailing list [email protected] https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
