On 28/06/11 11:43, Michael Schnell wrote:
On 06/28/2011 12:24 PM, Henry Vermaak wrote:
To add to this, on x86 the memory barrier is probably implemented with
an atomic instruction.
Like MUTEX/FUTEX (and critical section) on the system level all this
needs to be done using atomic (and with SMP bus locking / cache
invalidating) instructions (with no-SMP, disabling the interrupt would
be another system-level option).
Different architectures have specific memory barrier instructions which
must be used. For example, arm has DMB, DSB, ISB.
Henry
--
_______________________________________________
Lazarus mailing list
Lazarus@lists.lazarus.freepascal.org
http://lists.lazarus.freepascal.org/mailman/listinfo/lazarus
