On 06/28/2011 02:47 PM, Andrew Brunner wrote:
Yes, any object that requires atomic features will employ a memory
barrier.
That is to say the MB is employed in order for the spincount to be
accurate across all cores.
As for a user program the only way to handle atomic operations is to
protect them by a MUTEX (TCriticalSection in FPC) and same does include
the memory barrier we hopefully are safe.
My engine had worked fine on a tripple core AMD.
It wasn't until I upgraded to the 6 core system did I have to start
looking into what was causing random problems with pointer
assignments.
Of course it might be possible that it just was good luck that it worked
on the 3-Core (because the bad timing condition did not ever occur). But
there also might be some bug somewhere.
As said before besides all this complicated stuff the critical variable
needs to be handled as volatile by the compiler (not caching it in a
register while opening or closing the critical section). I have no Idea
how this can be enforced in FPC.
-Michael
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